Formal approaches to analog circuit verification

Erich Barke, Darius Grabowski, Helmut Graeb, Lars Hedrich, Stefan Heinen, Ralf Popp, Sebastian Steinhorst, Wang Yifan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

For a speed-up of analog design cycles to keep up with the continuously decreasing time to market, iterative design refinement and redesigns are more than ever regarded as showstoppers. To deal with this issue, referred to as design and verification gap, the development of a continuous and consistent verification is mandatory. In digital design, formal verification methods are considered as a key technology for efficient design flows. However, industrial availability of formal methods for analog circuit verification is still negligible despite a growing need. In recent years, research institutions have made considerable advances in the area of formal verification of analog circuits. This paper presents a selection of four recent approaches in analog verification that cover a broad scope of verification philosophies.

Original languageEnglish
Title of host publicationProceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages724-729
Number of pages6
ISBN (Print)9783981080155
DOIs
StatePublished - 2009
Externally publishedYes
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, France
Duration: 20 Apr 200924 Apr 2009

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
Country/TerritoryFrance
CityNice
Period20/04/0924/04/09

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