TY - GEN
T1 - Focus on What is Needed
T2 - 18th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
AU - Serajeh-Hassani, Fatemeh
AU - Sadrosadati, Mohammad
AU - Pointner, Sebastian
AU - Wille, Robert
AU - Sarbazi-Azad, Hamid
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Field-Programmable Gate Arrays (FPGAs) employ a significant amount of SRAM cells in order to provide a flexible routing architecture. While this flexibility allows for a rather easy realization of arbitrary functionality, the respectively required cells significantly increase the area and power consumption of the FPGA. At the same time, it can be observed that full routing flexibility is frequently not needed in order to efficiently realize the desired functionality. In this work, we are proposing an FPGA realization which focuses on what is needed and realizes only a subset of the possible routing options using what we call Turn-Restricted Switch-Boxes. While this may yield a slight decrease in the run-time performance of the realized functionality, it allows for substantial improvements with respect to area and power consumption. In fact, experimental evaluations confirm that area and power can be reduced by more than 40% and 60%, respectively, in the best cases. The performance overhead is negligible (up to 3%), on average.
AB - Field-Programmable Gate Arrays (FPGAs) employ a significant amount of SRAM cells in order to provide a flexible routing architecture. While this flexibility allows for a rather easy realization of arbitrary functionality, the respectively required cells significantly increase the area and power consumption of the FPGA. At the same time, it can be observed that full routing flexibility is frequently not needed in order to efficiently realize the desired functionality. In this work, we are proposing an FPGA realization which focuses on what is needed and realizes only a subset of the possible routing options using what we call Turn-Restricted Switch-Boxes. While this may yield a slight decrease in the run-time performance of the realized functionality, it allows for substantial improvements with respect to area and power consumption. In fact, experimental evaluations confirm that area and power can be reduced by more than 40% and 60%, respectively, in the best cases. The performance overhead is negligible (up to 3%), on average.
UR - http://www.scopus.com/inward/record.url?scp=85072972457&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2019.00115
DO - 10.1109/ISVLSI.2019.00115
M3 - Conference contribution
AN - SCOPUS:85072972457
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 615
EP - 620
BT - Proceedings - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019
PB - IEEE Computer Society
Y2 - 15 July 2019 through 17 July 2019
ER -