TY - GEN
T1 - FlexPath NP - A network processor concept with application-driven flexible processing paths
AU - Ohlendorf, Rainer
AU - Herkersdorf, Andreas
AU - Wild, Thomas
PY - 2005
Y1 - 2005
N2 - In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based System on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.
AB - In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based System on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.
KW - Application-specific architectures
KW - Dynamically reconfigurable processors
KW - Hardware accelerators
KW - IP networking
KW - Network processors
UR - http://www.scopus.com/inward/record.url?scp=27644529277&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:27644529277
SN - 1595931619
T3 - CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis
SP - 279
EP - 284
BT - CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis
T2 - 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005
Y2 - 18 September 2005 through 21 September 2005
ER -