Flexible VLSI architecture for variable block size segment matching with luminance correction

This paper describes a flexible 25.6 Giga operations per second exhaustive search segment matching VLSI architecture to support evolving motion estimation algorithms as well as block matching algorithms of established video coding standards. The architecture is based on a 16×16 processor element (PE) array and a 12 kbyte on-chip search area RAM and allows concurrent calculation of motion vectors for 32×32, 16×16, 8×8 and 4×4 blocks and partial quadtrees (called segments) for a +/-32 pel search range with 100% PE utilization. This architecture supports object based algorithms by excluding pixels outside of video objects from the segment matching process as well as advanced algorithms like variable blocksize segment matching with luminance correction. A preprocessing unit is included to support halfpel interpolation and pixel decimation. The VLSI has been designed using VHDL synthesis and a 0.5 μm CMOS technology. The chip will have a clock rate of 100 Mhz (min.) allowing realtime variable blocksize segment matching of 4CIF video (704×576 pel) at 15 fps or luminance corrected variable blocksize segment matching at above CIF (352×288), 15 fps resolution.