Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering

Michael Mildner, Michaela Brunner, Michael Gruber, Johanna Baehr, Georg Sigl

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This work outlines a crucial step in gate-level netlist reverse engineering: classifying control and data flip-flops (FFs) to discern control logic and data paths. Existing methods rely mainly on structural characteristics, which can have disavantages. Our work introduces a novel approach that classifies FFs based on observed characteristics after fault insertion and propagation. We develop three new classification methods for block cipher implementations, emphasizing their significance in system security. However, we also explore the approach's applicability to other design types. We apply the approach on AES implementations using an automatic fault simulation framework, which shows perfect results for most classifications.

Original languageEnglish
Title of host publicationProceedings - 2024 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2024
EditorsStanislaw Deniziak, Pawel Sitek, Maksim Jenihhin, Andreas Steininger, Mario Scholzel, Vojtech Mrazek
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages53-56
Number of pages4
ISBN (Electronic)9798350359343
DOIs
StatePublished - 2024
Externally publishedYes
Event27th International Symposium on Design and Diagnostics of Electronic Circuits and Sytems, DDECS 2024 - Kielce, Poland
Duration: 3 Apr 20245 Apr 2024

Publication series

NameProceedings - 2024 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2024

Conference

Conference27th International Symposium on Design and Diagnostics of Electronic Circuits and Sytems, DDECS 2024
Country/TerritoryPoland
CityKielce
Period3/04/245/04/24

Keywords

  • Block Cipher
  • Fault Simulation
  • Flip-Flop Classification
  • Hardware Reverse Engineering

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