Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers

Bing Li; Ning Chen; Ulf Schlichtmann

doi:10.1109/ICCAD.2011.6105314

Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers

Bing Li
, Ning Chen
, Ulf Schlichtmann

Chair of Electronic Design Automation

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

16 Scopus citations

Abstract

Post-Silicon Tunable (PST) clock buffers are widely used in high performance designs to counter process variations. By allowing delay compensation between consecutive register stages, PST buffers can effectively improve the yield of digital circuits. To date, the evaluation of manufacturing yield in the presence of PST buffers is only possible using Monte Carlo simulation. In this paper, we propose an alternative method based on graph transformations, which is much faster, more than 1000 times, and computes a parametric minimum clock period. It also identifies the gates which are most critical to the circuit performance, therefore enabling a fast analysis-optimization flow.

Original language	English
Title of host publication	2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
Pages	111-117
Number of pages	7
DOIs	https://doi.org/10.1109/ICCAD.2011.6105314
State	Published - 2011
Event	2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011 - San Jose, CA, United States Duration: 7 Nov 2011 → 10 Nov 2011

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)	1092-3152

Conference

Conference	2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
Country/Territory	United States
City	San Jose, CA
Period	7/11/11 → 10/11/11

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10.1109/ICCAD.2011.6105314

Cite this

Li, B., Chen, N., & Schlichtmann, U. (2011). Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers. In 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011 (pp. 111-117). Article 6105314 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD). https://doi.org/10.1109/ICCAD.2011.6105314

@inproceedings{6eaf698bba084a33ab3dfa88a89f9432,

title = "Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers",

abstract = "Post-Silicon Tunable (PST) clock buffers are widely used in high performance designs to counter process variations. By allowing delay compensation between consecutive register stages, PST buffers can effectively improve the yield of digital circuits. To date, the evaluation of manufacturing yield in the presence of PST buffers is only possible using Monte Carlo simulation. In this paper, we propose an alternative method based on graph transformations, which is much faster, more than 1000 times, and computes a parametric minimum clock period. It also identifies the gates which are most critical to the circuit performance, therefore enabling a fast analysis-optimization flow.",

author = "Bing Li and Ning Chen and Ulf Schlichtmann",

year = "2011",

doi = "10.1109/ICCAD.2011.6105314",

language = "English",

isbn = "9781457713989",

series = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD",

pages = "111--117",

booktitle = "2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011",

note = "2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011 ; Conference date: 07-11-2011 Through 10-11-2011",

}

Li, B, Chen, N & Schlichtmann, U 2011, Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers. in 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011., 6105314, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, pp. 111-117, 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011, San Jose, CA, United States, 7/11/11. https://doi.org/10.1109/ICCAD.2011.6105314

Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers. / Li, Bing; Chen, Ning; Schlichtmann, Ulf.
2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011. 2011. p. 111-117 6105314 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers

AU - Li, Bing

AU - Chen, Ning

AU - Schlichtmann, Ulf

PY - 2011

Y1 - 2011

N2 - Post-Silicon Tunable (PST) clock buffers are widely used in high performance designs to counter process variations. By allowing delay compensation between consecutive register stages, PST buffers can effectively improve the yield of digital circuits. To date, the evaluation of manufacturing yield in the presence of PST buffers is only possible using Monte Carlo simulation. In this paper, we propose an alternative method based on graph transformations, which is much faster, more than 1000 times, and computes a parametric minimum clock period. It also identifies the gates which are most critical to the circuit performance, therefore enabling a fast analysis-optimization flow.

AB - Post-Silicon Tunable (PST) clock buffers are widely used in high performance designs to counter process variations. By allowing delay compensation between consecutive register stages, PST buffers can effectively improve the yield of digital circuits. To date, the evaluation of manufacturing yield in the presence of PST buffers is only possible using Monte Carlo simulation. In this paper, we propose an alternative method based on graph transformations, which is much faster, more than 1000 times, and computes a parametric minimum clock period. It also identifies the gates which are most critical to the circuit performance, therefore enabling a fast analysis-optimization flow.

UR - https://www.scopus.com/pages/publications/84862923934

U2 - 10.1109/ICCAD.2011.6105314

DO - 10.1109/ICCAD.2011.6105314

M3 - Conference contribution

AN - SCOPUS:84862923934

SN - 9781457713989

T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

SP - 111

EP - 117

BT - 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011

T2 - 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011

Y2 - 7 November 2011 through 10 November 2011

ER -

Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers

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