Abstract
A methodology is proposed for glitch-free power switching of unused circuit blocks in leakage dominated deep-submicrometre technologies. With respect to conventional non-glitch-free approaches, significantly faster settling time and lower power consumption during the activation of the block are obtained.
Original language | English |
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Pages (from-to) | 103-104 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 40 |
Issue number | 2 |
DOIs | |
State | Published - 22 Jan 2004 |