Abstract
The authors combine the well-known concept of restricting fault simulation to the fanout stems with a critical path tracing method inside the fanout-free regions of the circuit. On this basis, proposals are made to further accelerate fault simulation and fault grading. These proposals aim at a parallel evaluation of the binary signal values by utilizing the full length of machine words for bit-string operations. The proposals are also directed at a reduction of the number of fanout stems for which a fault simulation has to be carried out.
| Original language | English |
|---|---|
| Title of host publication | Unknown Host Publication Title |
| Publisher | IEEE |
| Pages | 330-333 |
| Number of pages | 4 |
| ISBN (Print) | 0818607440 |
| State | Published - 1986 |