Fast automatic sizing of a charge pump phase-locked loop based on behavioral models

Jun Zou, Daniel Mueller, Helmut Graeb, Ulf Schlichtmann, Eckhard Hennig, Ralf Sommer

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

In this paper, we present an analog hierarchical sizing methodology applied to a third-order charge pump phase-locked loop (CPPLL). The key idea is to propagate the specifications from the requirements of the behavioral level to the circuit level. At the behavioral level, the performance is optimized while considering the potential capacity of the underlying circuits. Critical advantage of the illustrated methodology is a shortened PLL sizing process due to the use of fast-simulating models at behavioral level. The simulation results show the availability of this method on the CPPLL which makes an automatic sizing process actually feasible in terms of computation time.

Original languageEnglish
Title of host publicationBMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop
Pages100-105
Number of pages6
DOIs
StatePublished - 2005
EventBMAS 2005 - 2005 IEEE International Behavioral Modeling and Simulation Workshop - San Jose, CA, United States
Duration: 22 Sep 200523 Sep 2005

Publication series

NameBMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop
Volume2005

Conference

ConferenceBMAS 2005 - 2005 IEEE International Behavioral Modeling and Simulation Workshop
Country/TerritoryUnited States
CitySan Jose, CA
Period22/09/0523/09/05

Keywords

  • Behavioral Modeling
  • Bottom-Up
  • Hierarchical Sizing
  • Locking Time
  • Phase Margin
  • Top-Down

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