Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions

A. Icaza Deckelmann; G. Wachutka; J. Krumrey; F. Hirler; R. Henninger

doi:10.1109/EDSSC.2003.1283537

Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions

A. Icaza Deckelmann, G. Wachutka, J. Krumrey, F. Hirler, R. Henninger

Computation, Information and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The failure of power DMOS transistor arrays under unclamped inductive switching- (UIS-) stress conditions is investigated using continous field-based electrothermal device simulation. With reference to previous work of the authors, progressively deeper insight into the failure mechanism enables its detailed understanding. The temperature and current distributions among parallel DMOS cells in the array indicate that indeed the simulation of one single cell can be used as a reliable means of assessing the safe operating area (SOA) of the transistor array under UIS stress conditions. A comparison with measured data shows reasonable agreement with the simulation results and, thus, corroborates the validity of our model.

Original language	English
Title of host publication	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	305-308
Number of pages	4
ISBN (Electronic)	0780377494, 9780780377493
DOIs	https://doi.org/10.1109/EDSSC.2003.1283537
State	Published - 2003
Event	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong Duration: 16 Dec 2003 → 18 Dec 2003

Publication series

Name	2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Conference

Conference	IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
Country/Territory	Hong Kong
City	Tsimshatsui, Kowloon
Period	16/12/03 → 18/12/03

Access to Document

10.1109/EDSSC.2003.1283537

Cite this

Icaza Deckelmann, A., Wachutka, G., Krumrey, J., Hirler, F., & Henninger, R. (2003). Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 305-308). Article 1283537 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283537

Icaza Deckelmann, A. ; Wachutka, G. ; Krumrey, J. et al. / Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions. 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 305-308 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

@inproceedings{30cc0ce6e49d46ebbff5ac4d8a4c893b,

title = "Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions",

abstract = "The failure of power DMOS transistor arrays under unclamped inductive switching- (UIS-) stress conditions is investigated using continous field-based electrothermal device simulation. With reference to previous work of the authors, progressively deeper insight into the failure mechanism enables its detailed understanding. The temperature and current distributions among parallel DMOS cells in the array indicate that indeed the simulation of one single cell can be used as a reliable means of assessing the safe operating area (SOA) of the transistor array under UIS stress conditions. A comparison with measured data shows reasonable agreement with the simulation results and, thus, corroborates the validity of our model.",

author = "{Icaza Deckelmann}, A. and G. Wachutka and J. Krumrey and F. Hirler and R. Henninger",

note = "Publisher Copyright: {\textcopyright}2003 IEEE.; IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 ; Conference date: 16-12-2003 Through 18-12-2003",

year = "2003",

doi = "10.1109/EDSSC.2003.1283537",

language = "English",

series = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "305--308",

booktitle = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",

}

Icaza Deckelmann, A, Wachutka, G, Krumrey, J, Hirler, F & Henninger, R 2003, Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283537, 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 305-308, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 16/12/03. https://doi.org/10.1109/EDSSC.2003.1283537

Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions. / Icaza Deckelmann, A.; Wachutka, G.; Krumrey, J. et al.
2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 305-308 1283537 (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions

AU - Icaza Deckelmann, A.

AU - Wachutka, G.

AU - Krumrey, J.

AU - Hirler, F.

AU - Henninger, R.

PY - 2003

Y1 - 2003

N2 - The failure of power DMOS transistor arrays under unclamped inductive switching- (UIS-) stress conditions is investigated using continous field-based electrothermal device simulation. With reference to previous work of the authors, progressively deeper insight into the failure mechanism enables its detailed understanding. The temperature and current distributions among parallel DMOS cells in the array indicate that indeed the simulation of one single cell can be used as a reliable means of assessing the safe operating area (SOA) of the transistor array under UIS stress conditions. A comparison with measured data shows reasonable agreement with the simulation results and, thus, corroborates the validity of our model.

AB - The failure of power DMOS transistor arrays under unclamped inductive switching- (UIS-) stress conditions is investigated using continous field-based electrothermal device simulation. With reference to previous work of the authors, progressively deeper insight into the failure mechanism enables its detailed understanding. The temperature and current distributions among parallel DMOS cells in the array indicate that indeed the simulation of one single cell can be used as a reliable means of assessing the safe operating area (SOA) of the transistor array under UIS stress conditions. A comparison with measured data shows reasonable agreement with the simulation results and, thus, corroborates the validity of our model.

UR - http://www.scopus.com/inward/record.url?scp=84946423252&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2003.1283537

DO - 10.1109/EDSSC.2003.1283537

M3 - Conference contribution

AN - SCOPUS:84946423252

T3 - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

SP - 305

EP - 308

BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

Y2 - 16 December 2003 through 18 December 2003

ER -

Icaza Deckelmann A, Wachutka G, Krumrey J, Hirler F, Henninger R. Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 305-308. 1283537. (2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003). doi: 10.1109/EDSSC.2003.1283537

Failure of power DMOS transistor arrays under unclamped inductive switching stress conditions

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this