Failure of multiple-cell power DMOS transistors in avalanche operation

A. Icaza Deckelmann; G. Wachutka; F. Hirler; J. Krumrey; R. Henninger

doi:10.1109/ESSDERC.2003.1256879

Failure of multiple-cell power DMOS transistors in avalanche operation

A. Icaza Deckelmann
, G. Wachutka
, F. Hirler
, J. Krumrey
, R. Henninger

Computation, Information and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

We continued the work presented in [1], showing by multiple-cell device simulation that the failure mechanism found for a single DMOS transistor cell, , indeed applies to a multiple-cell array, when the simplified model is extended to the whole device Structure. Moreover, the current crowding phenomenon predicted by the model in [1] is corroboraied by experimental failure analysis. Current filamentation, which had already been indicated by 2D-simulation could now be demonstrated by means of 3D-simulation. In this context, it showed that a physically rigorous electrothermal transport model is mandatory in order to achieve a good agreement with experimental data.

Original language	English
Title of host publication	ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference
Editors	Jose Franca, Paulo Freitas
Publisher	IEEE Computer Society
Pages	323-326
Number of pages	4
ISBN (Electronic)	0780379993
ISBN (Print)	9780780379992
DOIs	https://doi.org/10.1109/ESSDERC.2003.1256879
State	Published - 2003
Event	33rd European Solid-State Device Research Conference, ESSDERC 2003 - Estoril, Portugal Duration: 16 Sep 2003 → 18 Sep 2003

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	33rd European Solid-State Device Research Conference, ESSDERC 2003
Country/Territory	Portugal
City	Estoril
Period	16/09/03 → 18/09/03

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10.1109/ESSDERC.2003.1256879

Cite this

Icaza Deckelmann, A., Wachutka, G., Hirler, F., Krumrey, J., & Henninger, R. (2003). Failure of multiple-cell power DMOS transistors in avalanche operation. In J. Franca, & P. Freitas (Eds.), ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference (pp. 323-326). Article 1256879 (European Solid-State Device Research Conference). IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2003.1256879

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title = "Failure of multiple-cell power DMOS transistors in avalanche operation",

abstract = "We continued the work presented in [1], showing by multiple-cell device simulation that the failure mechanism found for a single DMOS transistor cell, , indeed applies to a multiple-cell array, when the simplified model is extended to the whole device Structure. Moreover, the current crowding phenomenon predicted by the model in [1] is corroboraied by experimental failure analysis. Current filamentation, which had already been indicated by 2D-simulation could now be demonstrated by means of 3D-simulation. In this context, it showed that a physically rigorous electrothermal transport model is mandatory in order to achieve a good agreement with experimental data.",

author = "\{Icaza Deckelmann\}, A. and G. Wachutka and F. Hirler and J. Krumrey and R. Henninger",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 33rd European Solid-State Device Research Conference, ESSDERC 2003 ; Conference date: 16-09-2003 Through 18-09-2003",

year = "2003",

doi = "10.1109/ESSDERC.2003.1256879",

language = "English",

isbn = "9780780379992",

series = "European Solid-State Device Research Conference",

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Icaza Deckelmann, A, Wachutka, G, Hirler, F, Krumrey, J & Henninger, R 2003, Failure of multiple-cell power DMOS transistors in avalanche operation. in J Franca & P Freitas (eds), ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference., 1256879, European Solid-State Device Research Conference, IEEE Computer Society, pp. 323-326, 33rd European Solid-State Device Research Conference, ESSDERC 2003, Estoril, Portugal, 16/09/03. https://doi.org/10.1109/ESSDERC.2003.1256879

Failure of multiple-cell power DMOS transistors in avalanche operation. / Icaza Deckelmann, A.; Wachutka, G.; Hirler, F. et al.
ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference. ed. / Jose Franca; Paulo Freitas. IEEE Computer Society, 2003. p. 323-326 1256879 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Failure of multiple-cell power DMOS transistors in avalanche operation

AU - Icaza Deckelmann, A.

AU - Wachutka, G.

AU - Hirler, F.

AU - Krumrey, J.

AU - Henninger, R.

PY - 2003

Y1 - 2003

N2 - We continued the work presented in [1], showing by multiple-cell device simulation that the failure mechanism found for a single DMOS transistor cell, , indeed applies to a multiple-cell array, when the simplified model is extended to the whole device Structure. Moreover, the current crowding phenomenon predicted by the model in [1] is corroboraied by experimental failure analysis. Current filamentation, which had already been indicated by 2D-simulation could now be demonstrated by means of 3D-simulation. In this context, it showed that a physically rigorous electrothermal transport model is mandatory in order to achieve a good agreement with experimental data.

AB - We continued the work presented in [1], showing by multiple-cell device simulation that the failure mechanism found for a single DMOS transistor cell, , indeed applies to a multiple-cell array, when the simplified model is extended to the whole device Structure. Moreover, the current crowding phenomenon predicted by the model in [1] is corroboraied by experimental failure analysis. Current filamentation, which had already been indicated by 2D-simulation could now be demonstrated by means of 3D-simulation. In this context, it showed that a physically rigorous electrothermal transport model is mandatory in order to achieve a good agreement with experimental data.

UR - https://www.scopus.com/pages/publications/79951623268

U2 - 10.1109/ESSDERC.2003.1256879

DO - 10.1109/ESSDERC.2003.1256879

M3 - Conference contribution

AN - SCOPUS:79951623268

SN - 9780780379992

T3 - European Solid-State Device Research Conference

SP - 323

EP - 326

BT - ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference

A2 - Franca, Jose

A2 - Freitas, Paulo

PB - IEEE Computer Society

T2 - 33rd European Solid-State Device Research Conference, ESSDERC 2003

Y2 - 16 September 2003 through 18 September 2003

ER -

Icaza Deckelmann A, Wachutka G, Hirler F, Krumrey J, Henninger R. Failure of multiple-cell power DMOS transistors in avalanche operation. In Franca J, Freitas P, editors, ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference. IEEE Computer Society. 2003. p. 323-326. 1256879. (European Solid-State Device Research Conference). doi: 10.1109/ESSDERC.2003.1256879

Failure of multiple-cell power DMOS transistors in avalanche operation

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