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Failure mechanism of power DMOS transistors under UIS stress conditions

  • A. Icaza-Deckelmann
  • , G. Wachutka
  • , J. Krumrey
  • , F. Hirler
  • Technical University of Munich
  • Infineon Technologies AG

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

The failure mechanism of multiple-cell power DMOS transistors under UIS stress conditions, where the device current is imposed by the external circuit, is investigated by means of electrothermal device simulation. The results suggest that the failure is caused by the concentration of the each cell's current in a bipolar transistor structure. In the simulation, a strong temperature rise precedes this pattern formation, within application-relevant current levels. Our analysis shows that the heat generated by the high current density may lead to an instability, and that subsequently the device current is likely to concentrate in one single cell of the device, producing eventual failure.

Original languageEnglish
Title of host publicationASDAM 2002 - Conference Proceedings, 4th International Conference on Advanced Semiconductor Devices and Microsystems
EditorsDaniel Donoval, Juraj Breza
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages349-352
Number of pages4
ISBN (Electronic)078037276X, 9780780372764
DOIs
StatePublished - 2002
Event4th International Conference on Advanced Semiconductor Devices and Microsystems, ASDAM 2002 - Smolenice, Slovakia
Duration: 14 Oct 200216 Oct 2002

Publication series

NameASDAM 2002 - Conference Proceedings, 4th International Conference on Advanced Semiconductor Devices and Microsystems

Conference

Conference4th International Conference on Advanced Semiconductor Devices and Microsystems, ASDAM 2002
Country/TerritorySlovakia
CitySmolenice
Period14/10/0216/10/02

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