Fabrication, optimization and application of complementary multiple-gate tunneling FETs

M. Fulde, A. Heigl, M. Weis, M. Wirnshofer, K. V. Arnim, Th Nirschl, M. Sterkel, G. Knoblinger, W. Hansch, G. Wachutka, D. Schmitt-Landsiedel

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

25 Scopus citations

Abstract

We present fabrication, optimization and application aspects of complementary Multiple-Gate Tunneling FETs (MuGTFETs). Tunneling FETs are implemented in a MuGFET technology for the first time. N- and p-type tunneling currents are observed within a single device structure. Digital and analog device performance is analyzed. Measured devices show low on-currents in the tens of nA regime due to not optimized doping profiles. However, promising analog characteristics are obtained with intrinsic gain of more than 300 for 65nm channel length devices. The scaling potential of multi-gate tunneling FETs is proven by measurements and device simulations that reveal a low dependence of the device characteristics on the channel length. The devices feature low temperature dependence and competitive matching behavior. A new voltage reference circuit is proposed as potential application for the MuGTFET.

Original languageEnglish
Title of host publication2008 2nd IEEE International Nanoelectronics Conference, INEC 2008
Pages579-584
Number of pages6
DOIs
StatePublished - 2008
Event2008 2nd IEEE International Nanoelectronics Conference, INEC 2008 - Shanghai, China
Duration: 24 Mar 200827 Mar 2008

Publication series

Name2008 2nd IEEE International Nanoelectronics Conference, INEC 2008

Conference

Conference2008 2nd IEEE International Nanoelectronics Conference, INEC 2008
Country/TerritoryChina
CityShanghai
Period24/03/0827/03/08

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