Fabrication, optimization and application of complementary multiple-gate tunneling FETs

M. Fulde; A. Heigl; M. Weis; M. Wirnshofer; K. V. Arnim; Th Nirschl; M. Sterkel; G. Knoblinger; W. Hansch; G. Wachutka; D. Schmitt-Landsiedel

doi:10.1109/INEC.2008.4585554

Fabrication, optimization and application of complementary multiple-gate tunneling FETs

M. Fulde, A. Heigl, M. Weis, M. Wirnshofer, K. V. Arnim, Th Nirschl, M. Sterkel, G. Knoblinger, W. Hansch, G. Wachutka, D. Schmitt-Landsiedel

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

26 Scopus citations

Abstract

We present fabrication, optimization and application aspects of complementary Multiple-Gate Tunneling FETs (MuGTFETs). Tunneling FETs are implemented in a MuGFET technology for the first time. N- and p-type tunneling currents are observed within a single device structure. Digital and analog device performance is analyzed. Measured devices show low on-currents in the tens of nA regime due to not optimized doping profiles. However, promising analog characteristics are obtained with intrinsic gain of more than 300 for 65nm channel length devices. The scaling potential of multi-gate tunneling FETs is proven by measurements and device simulations that reveal a low dependence of the device characteristics on the channel length. The devices feature low temperature dependence and competitive matching behavior. A new voltage reference circuit is proposed as potential application for the MuGTFET.

Original language	English
Title of host publication	2008 2nd IEEE International Nanoelectronics Conference, INEC 2008
Pages	579-584
Number of pages	6
DOIs	https://doi.org/10.1109/INEC.2008.4585554
State	Published - 2008
Event	2008 2nd IEEE International Nanoelectronics Conference, INEC 2008 - Shanghai, China Duration: 24 Mar 2008 → 27 Mar 2008

Publication series

Name	2008 2nd IEEE International Nanoelectronics Conference, INEC 2008

Conference

Conference	2008 2nd IEEE International Nanoelectronics Conference, INEC 2008
Country/Territory	China
City	Shanghai
Period	24/03/08 → 27/03/08

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10.1109/INEC.2008.4585554

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Fulde, M., Heigl, A., Weis, M., Wirnshofer, M., Arnim, K. V., Nirschl, T., Sterkel, M., Knoblinger, G., Hansch, W., Wachutka, G., & Schmitt-Landsiedel, D. (2008). Fabrication, optimization and application of complementary multiple-gate tunneling FETs. In 2008 2nd IEEE International Nanoelectronics Conference, INEC 2008 (pp. 579-584). Article 4585554 (2008 2nd IEEE International Nanoelectronics Conference, INEC 2008). https://doi.org/10.1109/INEC.2008.4585554

@inproceedings{30e1e1af1f0c4b65ac9b89399524ad72,

title = "Fabrication, optimization and application of complementary multiple-gate tunneling FETs",

abstract = "We present fabrication, optimization and application aspects of complementary Multiple-Gate Tunneling FETs (MuGTFETs). Tunneling FETs are implemented in a MuGFET technology for the first time. N- and p-type tunneling currents are observed within a single device structure. Digital and analog device performance is analyzed. Measured devices show low on-currents in the tens of nA regime due to not optimized doping profiles. However, promising analog characteristics are obtained with intrinsic gain of more than 300 for 65nm channel length devices. The scaling potential of multi-gate tunneling FETs is proven by measurements and device simulations that reveal a low dependence of the device characteristics on the channel length. The devices feature low temperature dependence and competitive matching behavior. A new voltage reference circuit is proposed as potential application for the MuGTFET.",

author = "M. Fulde and A. Heigl and M. Weis and M. Wirnshofer and Arnim, {K. V.} and Th Nirschl and M. Sterkel and G. Knoblinger and W. Hansch and G. Wachutka and D. Schmitt-Landsiedel",

year = "2008",

doi = "10.1109/INEC.2008.4585554",

language = "English",

isbn = "9781424415731",

series = "2008 2nd IEEE International Nanoelectronics Conference, INEC 2008",

pages = "579--584",

booktitle = "2008 2nd IEEE International Nanoelectronics Conference, INEC 2008",

note = "2008 2nd IEEE International Nanoelectronics Conference, INEC 2008 ; Conference date: 24-03-2008 Through 27-03-2008",

}

Fulde, M, Heigl, A, Weis, M, Wirnshofer, M, Arnim, KV, Nirschl, T, Sterkel, M, Knoblinger, G, Hansch, W, Wachutka, G & Schmitt-Landsiedel, D 2008, Fabrication, optimization and application of complementary multiple-gate tunneling FETs. in 2008 2nd IEEE International Nanoelectronics Conference, INEC 2008., 4585554, 2008 2nd IEEE International Nanoelectronics Conference, INEC 2008, pp. 579-584, 2008 2nd IEEE International Nanoelectronics Conference, INEC 2008, Shanghai, China, 24/03/08. https://doi.org/10.1109/INEC.2008.4585554

Fabrication, optimization and application of complementary multiple-gate tunneling FETs. / Fulde, M.; Heigl, A.; Weis, M. et al.
2008 2nd IEEE International Nanoelectronics Conference, INEC 2008. 2008. p. 579-584 4585554 (2008 2nd IEEE International Nanoelectronics Conference, INEC 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Fulde, M.

AU - Heigl, A.

AU - Weis, M.

AU - Wirnshofer, M.

AU - Arnim, K. V.

AU - Nirschl, Th

AU - Sterkel, M.

AU - Knoblinger, G.

AU - Hansch, W.

AU - Wachutka, G.

AU - Schmitt-Landsiedel, D.

PY - 2008

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N2 - We present fabrication, optimization and application aspects of complementary Multiple-Gate Tunneling FETs (MuGTFETs). Tunneling FETs are implemented in a MuGFET technology for the first time. N- and p-type tunneling currents are observed within a single device structure. Digital and analog device performance is analyzed. Measured devices show low on-currents in the tens of nA regime due to not optimized doping profiles. However, promising analog characteristics are obtained with intrinsic gain of more than 300 for 65nm channel length devices. The scaling potential of multi-gate tunneling FETs is proven by measurements and device simulations that reveal a low dependence of the device characteristics on the channel length. The devices feature low temperature dependence and competitive matching behavior. A new voltage reference circuit is proposed as potential application for the MuGTFET.

AB - We present fabrication, optimization and application aspects of complementary Multiple-Gate Tunneling FETs (MuGTFETs). Tunneling FETs are implemented in a MuGFET technology for the first time. N- and p-type tunneling currents are observed within a single device structure. Digital and analog device performance is analyzed. Measured devices show low on-currents in the tens of nA regime due to not optimized doping profiles. However, promising analog characteristics are obtained with intrinsic gain of more than 300 for 65nm channel length devices. The scaling potential of multi-gate tunneling FETs is proven by measurements and device simulations that reveal a low dependence of the device characteristics on the channel length. The devices feature low temperature dependence and competitive matching behavior. A new voltage reference circuit is proposed as potential application for the MuGTFET.

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BT - 2008 2nd IEEE International Nanoelectronics Conference, INEC 2008

T2 - 2008 2nd IEEE International Nanoelectronics Conference, INEC 2008

Y2 - 24 March 2008 through 27 March 2008

ER -

Fabrication, optimization and application of complementary multiple-gate tunneling FETs

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