Extracting logical structure and identifying stragglers in parallel execution traces

Katherine E. Isaacs, Todd Gamblin, Abhinav Bhatele, Peer Timo Bremer, Martin Schulz, Bernd Hamann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We introduce a new approach to automatically extract an idealized logical structure from a parallel execution trace. We use this structure to define intuitive metrics such as the lateness of a process involved in a parallel execution. By analyzing and illustrating traces in terms of logical steps, we leverage a developer's understanding of the happened-before relations in a parallel program. This technique can uncover dependency chains, elucidate communication patterns, and highlight sources and propagation of delays, all of which may be obscured in a traditional trace visualization.

Original languageEnglish
Title of host publicationPPoPP 2014 - Proceedings of the 2014 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
Pages397-398
Number of pages2
DOIs
StatePublished - 2014
Externally publishedYes
Event2014 19th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2014 - Orlando, FL, United States
Duration: 15 Feb 201419 Feb 2014

Publication series

NameProceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Conference

Conference2014 19th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2014
Country/TerritoryUnited States
CityOrlando, FL
Period15/02/1419/02/14

Keywords

  • Logical structure
  • Parallel execution trace
  • Visualization

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