Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs

Embedded systems for safety-critical application domains must provide fault-tolerance and hard real-time guarantees to critical applications as well as isolation of different applications from each other. These challenges have lead to a hesitant adoption of multi-core processors in such contexts. To address these issues for communication, we proposed a protection switching scheme for a hybrid TDM and packet-switched Network on Chip (NoC). The approach gives guarantees to critical applications but the remaining bandwidth for Best-Effort (BE) applications heavily depends on the channel and task mapping of the critical applications. In this paper we explore different channel and task mapping strategies for critical applications and evaluate the effect these mappings have on the BE traffic. We do the exploration on an FPGA prototype implementation by mapping different sets of critical task graphs on a tiled 8x8 system and measuring how much uniform random BE traffic can be transported in addition to the critical traffic. Results show that spreading out the critical traffic rather than strictly dividing the system in critical and non-critical applications domains is advantageous or even necessary in many cases and can increase the feasible BE traffic generation rate by up to 13x%.