Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy

Xiebing Wang; Linlin Liu; Kai Huang; Alois Knoll

doi:10.1007/978-3-319-65482-9_3

Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy

Xiebing Wang, Linlin Liu, Kai Huang, Alois Knoll

Informatics 6 - Chair of Robotics, Artificial Intelligence and Real-time Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

This paper investigates the feasibility of using heterogeneous computing for future advanced driver assistance systems (ADAS) applications. In particular, we take lane detection algorithm (LDA) as a test case. The algorithm is customized into FPGA-GPU heterogeneous implementations which can be executed in either workload constant or balanced scheme. Then the heterogeneous executions are evaluated in view of performance and energy consumption, and further compared with the single-accelerator run. Experiments show that the heterogeneous execution alleviates both the performance and energy bottlenecks caused when only using a single accelerator. Moreover, compared with the single FPGA execution, the workload balance scheme increases the performance by 236.9% and 42.9% on our two tested platforms respectively, while ensuring the low energy cost.

Original language	English
Title of host publication	Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Proceedings
Editors	Shadi Ibrahim, Zheng Yan, Kim-Kwang Raymond Choo, Witold Pedrycz
Publisher	Springer Verlag
Pages	33-48
Number of pages	16
ISBN (Print)	9783319654812
DOIs	https://doi.org/10.1007/978-3-319-65482-9_3
State	Published - 2017
Event	17th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2017 - Helsinki, Finland Duration: 21 Aug 2017 → 23 Aug 2017

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	10393 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	17th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2017
Country/Territory	Finland
City	Helsinki
Period	21/08/17 → 23/08/17

Keywords

Advanced driver assistance systems (ADAS)
FPGA
GPU
OpenCL

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1007/978-3-319-65482-9_3

Cite this

Wang, X., Liu, L., Huang, K., & Knoll, A. (2017). Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy. In S. Ibrahim, Z. Yan, K.-K. R. Choo, & W. Pedrycz (Eds.), Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Proceedings (pp. 33-48). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10393 LNCS). Springer Verlag. https://doi.org/10.1007/978-3-319-65482-9_3

Wang, Xiebing ; Liu, Linlin ; Huang, Kai et al. / Exploring FPGA-GPU heterogeneous architecture for ADAS : Towards performance and energy. Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Proceedings. editor / Shadi Ibrahim ; Zheng Yan ; Kim-Kwang Raymond Choo ; Witold Pedrycz. Springer Verlag, 2017. pp. 33-48 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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title = "Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy",

abstract = "This paper investigates the feasibility of using heterogeneous computing for future advanced driver assistance systems (ADAS) applications. In particular, we take lane detection algorithm (LDA) as a test case. The algorithm is customized into FPGA-GPU heterogeneous implementations which can be executed in either workload constant or balanced scheme. Then the heterogeneous executions are evaluated in view of performance and energy consumption, and further compared with the single-accelerator run. Experiments show that the heterogeneous execution alleviates both the performance and energy bottlenecks caused when only using a single accelerator. Moreover, compared with the single FPGA execution, the workload balance scheme increases the performance by 236.9% and 42.9% on our two tested platforms respectively, while ensuring the low energy cost.",

keywords = "Advanced driver assistance systems (ADAS), FPGA, GPU, OpenCL",

author = "Xiebing Wang and Linlin Liu and Kai Huang and Alois Knoll",

note = "Publisher Copyright: {\textcopyright} Springer International Publishing AG 2017.; 17th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2017 ; Conference date: 21-08-2017 Through 23-08-2017",

year = "2017",

doi = "10.1007/978-3-319-65482-9_3",

language = "English",

isbn = "9783319654812",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

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Wang, X, Liu, L, Huang, K & Knoll, A 2017, Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy. in S Ibrahim, Z Yan, K-KR Choo & W Pedrycz (eds), Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 10393 LNCS, Springer Verlag, pp. 33-48, 17th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2017, Helsinki, Finland, 21/08/17. https://doi.org/10.1007/978-3-319-65482-9_3

Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy. / Wang, Xiebing; Liu, Linlin; Huang, Kai et al.
Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Proceedings. ed. / Shadi Ibrahim; Zheng Yan; Kim-Kwang Raymond Choo; Witold Pedrycz. Springer Verlag, 2017. p. 33-48 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 10393 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Exploring FPGA-GPU heterogeneous architecture for ADAS

T2 - 17th International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2017

AU - Wang, Xiebing

AU - Liu, Linlin

AU - Huang, Kai

AU - Knoll, Alois

N1 - Publisher Copyright: © Springer International Publishing AG 2017.

PY - 2017

Y1 - 2017

N2 - This paper investigates the feasibility of using heterogeneous computing for future advanced driver assistance systems (ADAS) applications. In particular, we take lane detection algorithm (LDA) as a test case. The algorithm is customized into FPGA-GPU heterogeneous implementations which can be executed in either workload constant or balanced scheme. Then the heterogeneous executions are evaluated in view of performance and energy consumption, and further compared with the single-accelerator run. Experiments show that the heterogeneous execution alleviates both the performance and energy bottlenecks caused when only using a single accelerator. Moreover, compared with the single FPGA execution, the workload balance scheme increases the performance by 236.9% and 42.9% on our two tested platforms respectively, while ensuring the low energy cost.

AB - This paper investigates the feasibility of using heterogeneous computing for future advanced driver assistance systems (ADAS) applications. In particular, we take lane detection algorithm (LDA) as a test case. The algorithm is customized into FPGA-GPU heterogeneous implementations which can be executed in either workload constant or balanced scheme. Then the heterogeneous executions are evaluated in view of performance and energy consumption, and further compared with the single-accelerator run. Experiments show that the heterogeneous execution alleviates both the performance and energy bottlenecks caused when only using a single accelerator. Moreover, compared with the single FPGA execution, the workload balance scheme increases the performance by 236.9% and 42.9% on our two tested platforms respectively, while ensuring the low energy cost.

KW - Advanced driver assistance systems (ADAS)

KW - FPGA

KW - GPU

KW - OpenCL

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DO - 10.1007/978-3-319-65482-9_3

M3 - Conference contribution

AN - SCOPUS:85028456235

SN - 9783319654812

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 33

EP - 48

BT - Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Proceedings

A2 - Ibrahim, Shadi

A2 - Yan, Zheng

A2 - Choo, Kim-Kwang Raymond

A2 - Pedrycz, Witold

PB - Springer Verlag

Y2 - 21 August 2017 through 23 August 2017

ER -

Wang X, Liu L, Huang K, Knoll A. Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy. In Ibrahim S, Yan Z, Choo KKR, Pedrycz W, editors, Algorithms and Architectures for Parallel Processing - 17th International Conference, ICA3PP 2017, Proceedings. Springer Verlag. 2017. p. 33-48. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-319-65482-9_3

Exploring FPGA-GPU heterogeneous architecture for ADAS: Towards performance and energy

Abstract

Publication series

Conference

Keywords

UN SDGs

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