Exploiting state-of-the-art x86 architectures in scientific computing

Alexander Heinecke, Thomas Auckenthaler, Carsten Trinitis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In recent years, general purpose x86 architectures have undergone significant modifications towards high performance computing capabilities. Lately, technologies like wider vector units or Fused Multiply-Add (FMA) instruction, which were mainly known from GPU arcitectures, have been introduced. In this paper, we examine the performance of current x86 architectures, namely Intel Sandy Bridge and AMD Bulldozer, for four different parallel workloads with different properties. These properties comprise optimally cache-blocked algorithms as well as adaptive grid structures resulting in memory latency and bandwidth bound executions. The achieved performance on both architectures is very promising, and, if extrapolated towards upcoming server silicon, can be regarded as on par with current high-end GPU based accelerators.

Original languageEnglish
Title of host publicationProceedings - 2012 11th International Symposium on Parallel and Distributed Computing, ISPDC 2012
Pages47-54
Number of pages8
DOIs
StatePublished - 2012
Event2012 11th International Symposium on Parallel and Distributed Computing, ISPDC 2012 - Munich/Garching, Bavaria, Germany
Duration: 25 Jun 201229 Jun 2012

Publication series

NameProceedings - 2012 11th International Symposium on Parallel and Distributed Computing, ISPDC 2012

Conference

Conference2012 11th International Symposium on Parallel and Distributed Computing, ISPDC 2012
Country/TerritoryGermany
CityMunich/Garching, Bavaria
Period25/06/1229/06/12

Keywords

  • AMD
  • CPU architectures
  • Intel
  • Multi-core
  • parallel applications
  • vectorization

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