Abstract
We investigate the matching behavior of poly-silicon resistors. Experimental results from an analog CMOS process with three poly-silicon options are discussed and compared with a quantitative model which is developed using fit parameter-free analytical calculations and Monte-Carlo simulations. It is found that mismatch is directly proportional to the grain size. A relation is derived that allows to optimize devices for low mismatch circuit applications.
Original language | English |
---|---|
Pages (from-to) | 771-774 |
Number of pages | 4 |
Journal | Technical Digest - International Electron Devices Meeting |
State | Published - 1998 |
Externally published | Yes |
Event | Proceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA Duration: 6 Dec 1998 → 9 Dec 1998 |