ETTORE: A 12-Channel Front-End ASIC for SDDs with Integrated JFET

The present work describes the front-end analog electronics for the electron detector of the TRISTAN Project, aimed at the search of the keV-scale sterile neutrinos by means of spectroscopy of the tritium β-decay with unprecedented accuracy. In this framework, a 12-channel prototype ASIC for the readout of an array of SDDs with integrated nJFET has been developed.The channel comprises a preamplifier, forming a feedback loop with the transistor and charge integration capacitor both integrated on the detector chip, a comparator to detect the saturation of the output ramp-like voltage, a second AC-coupled amplifier with a 15 μs exponential decay, and capable to drive the external ADC. To allow a good pile-up rejection, needed to cope with the high electron rates of the experiment, an output rise time below 50 ns has been targeted as performance for the channel, even in presence of capacitive loads up to 70 pF, caused by the foreseen long tracks connecting the detector JFET to the ASIC. The ASIC has been realized in 0.35 μm AMS CMOS technology, with an overall area of about 6.5 mm², and has a power consumption of 15 mW/channel.Preliminary measurements performed with a circular SDD have shown an overall behavior in line with design expectations. The measured performances - a rise time below 40 ns, no crosstalk, and an energy resolution at the Mn-Kα line of 127 eV FWHM - are compliant with the project requirements.