TY - GEN
T1 - Envisioning Physical Layer Flexibility Through the Power of Machine-Learning
AU - Petry, Michael
AU - Koch, Andreas
AU - Werner, Martin
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper presents the vision of an adaptive radio frequency (RF) communication signal processing pipeline solely composed of machine learning domain operations, aiming to provide a fully hardware-accelerated alternative to dedicated RF chips. A hybrid architecture, comprising elements of classic signal processing and learnable algorithms trained in an end-to-end manner, is proposed, that is compatible with contemporary ML hardware accelerators. The RF -ML pipeline, including speed-up optimization modifications, are explained in detail, followed by a brief description summarizing the deployment workflow of the end-to-end system on a pair of AI-enabled space-grade FPGAs. Finally, a bit-error- rate performance study of the simulated system as well as a HW -deployed setup including software-defined radios (SDR) validates the concept, followed by a detailed throughput benchmark over multiple AI-accelerator hardware configurations. Finally, we raise questions regarding practical implementation, such as receiver synchronization, restrictions of the ML-accelerator feature space, and weight quantization, which are discussed at the end of this paper.
AB - This paper presents the vision of an adaptive radio frequency (RF) communication signal processing pipeline solely composed of machine learning domain operations, aiming to provide a fully hardware-accelerated alternative to dedicated RF chips. A hybrid architecture, comprising elements of classic signal processing and learnable algorithms trained in an end-to-end manner, is proposed, that is compatible with contemporary ML hardware accelerators. The RF -ML pipeline, including speed-up optimization modifications, are explained in detail, followed by a brief description summarizing the deployment workflow of the end-to-end system on a pair of AI-enabled space-grade FPGAs. Finally, a bit-error- rate performance study of the simulated system as well as a HW -deployed setup including software-defined radios (SDR) validates the concept, followed by a detailed throughput benchmark over multiple AI-accelerator hardware configurations. Finally, we raise questions regarding practical implementation, such as receiver synchronization, restrictions of the ML-accelerator feature space, and weight quantization, which are discussed at the end of this paper.
KW - fpga
KW - hardware acceleration
KW - machine learning
KW - physical layer
KW - signal processing
KW - software-defined radio
UR - http://www.scopus.com/inward/record.url?scp=85190234471&partnerID=8YFLogxK
U2 - 10.1109/GCWkshps58843.2023.10464871
DO - 10.1109/GCWkshps58843.2023.10464871
M3 - Conference contribution
AN - SCOPUS:85190234471
T3 - 2023 IEEE Globecom Workshops, GC Wkshps 2023
SP - 50
EP - 55
BT - 2023 IEEE Globecom Workshops, GC Wkshps 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE Globecom Workshops, GC Wkshps 2023
Y2 - 4 December 2023 through 8 December 2023
ER -