Enhancing debugging of multiple missing control errors in reversible logic

Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations


Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising direction so that several methods for synthesis, verification, and testing of reversible circuits have already been proposed. However, also methods for debugging, i.e., to determine error candidates in case of a failed verification, are required to complete the design flow. Even if first approaches have already been proposed, debugging of reversible circuits still is in the beginning. In this paper, we present an alternative method to automatically debug reversible circuits. We thereby focus on missing control errors - an established error model in the design of reversible circuits. A new notion of an error candidate is proposed that relies on the observation of a necessary condition for error locations in reversible circuits. Using this notion, a set of error candidates is obtained that differs from the error candidates returned by previous methods. Thus, combining the approaches enhances the overall debugging flow. Experimental results demonstrate that a higher accuracy is obtained in significantly shorter run-time.

Original languageEnglish
Title of host publicationGLSVLSI'10 - Proceedings of the Great Lakes Symposium on VLSI 2010
Number of pages6
StatePublished - 2010
Externally publishedYes
Event20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, United States
Duration: 16 May 201018 May 2010

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI


Conference20th Great Lakes Symposium on VLSI, GLSVLSI 2010
Country/TerritoryUnited States
CityProvidence, RI


  • boolean satisfiablity (SAT)
  • debugging
  • reversible logic


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