TY - GEN
T1 - Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping
AU - Listl, Alexandra
AU - Mueller-Gritschneder, Daniel
AU - Kluge, Fabian
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/9/26
Y1 - 2018/9/26
N2 - Technology scaling has enabled the fabrication of Multi-Processor Systems-on-Chips (MPSoCs), which satisfy the ever growing demand for performance, while continuously reducing the chip size. Thus, scaling has also led to new challenges such as increasing power densities, which critically influence the chip temperatures and accelerate device degradation due to aging. Runtime power management can be utilized to counter these reliability threats to increase the lifetime of a system. For the development of runtime power management strategies monitoring data for power, temperature and aging is required. In this paper we propose a real-time power, temperature and aging monitor system (eTAPMon) for FPGA prototypes of MPSoCs. The monitor system emulates data characterized from the target ASIC design. The emulation approach models the behavior of ASIC power monitors based on an instruction-level energy model, temperature monitors based on a linear regression model obtained from thermal offline simulations and aging monitors based on a critical path model to compute the decreasing timing margin due to aging. An accelerated aging emulation is possible to predict aged ASIC behavior. Hence, this FPGA emulation enables the early evaluation of runtime power management strategies.
AB - Technology scaling has enabled the fabrication of Multi-Processor Systems-on-Chips (MPSoCs), which satisfy the ever growing demand for performance, while continuously reducing the chip size. Thus, scaling has also led to new challenges such as increasing power densities, which critically influence the chip temperatures and accelerate device degradation due to aging. Runtime power management can be utilized to counter these reliability threats to increase the lifetime of a system. For the development of runtime power management strategies monitoring data for power, temperature and aging is required. In this paper we propose a real-time power, temperature and aging monitor system (eTAPMon) for FPGA prototypes of MPSoCs. The monitor system emulates data characterized from the target ASIC design. The emulation approach models the behavior of ASIC power monitors based on an instruction-level energy model, temperature monitors based on a linear regression model obtained from thermal offline simulations and aging monitors based on a critical path model to compute the decreasing timing margin due to aging. An accelerated aging emulation is possible to predict aged ASIC behavior. Hence, this FPGA emulation enables the early evaluation of runtime power management strategies.
KW - ASIC monitor emulation
KW - aging monitoring
KW - monitoring systems
KW - online monitoring
KW - power monitoring
KW - temperature monitoring
UR - http://www.scopus.com/inward/record.url?scp=85055767600&partnerID=8YFLogxK
U2 - 10.1109/IOLTS.2018.8474284
DO - 10.1109/IOLTS.2018.8474284
M3 - Conference contribution
AN - SCOPUS:85055767600
T3 - 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018
SP - 220
EP - 225
BT - 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018
A2 - Maniatakos, Mihalis
A2 - Alexandrescu, Dan
A2 - Gizopoulos, Dimitris
A2 - Papavramidou, Panagiota
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2018
Y2 - 2 July 2018 through 4 July 2018
ER -