Eine flexible Simulationsumgebung für System-On-Chip Design

Translated title of the contribution: A Flexible Simulation Environment for System-On-Chip Design

Andre Windisch, Thomas Schneider, Jochen Mades, Dieter Monjau, Manfred Glesner, Carsten Hammer, Wolfgang Ecker

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


The design of heterogeneous systems-on-chip (SoC) is accomplished by a hierarchical composition of interacting subsystems. These subsystems are typically modeled in various domain-specific languages thus resulting in a multi-language system specification. This design approach differs from traditional design methods for homogeneous digital system, which are usually modeled in a single hardware description language on register transfer level. Therefore, the design of complex heterogeneous systems requires the development of new design tools. This article presents a newly developed design environment which supports simulation of multi-lingual system specifications in VHDL-AMS, Java, and C++.

Translated title of the contributionA Flexible Simulation Environment for System-On-Chip Design
Original languageGerman
Pages (from-to)43-53
Number of pages11
JournalIT - Information Technology
Issue number5
StatePublished - 1 May 2000
Externally publishedYes


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