Efficient high-speed interface verification and fault analysis

In this article we discuss three challenges of device verification and test for high-speed interfaces, with special focus on latest memory device interface generations as DDR3 / GDDR5 / XDR working in the GHz clock frequency range. We address how efficient device verification in terms of reaching target coverage fast can be achieved through random methods on ATE, both random operating condition tests and Random Test Pattern (RTP). We present a novel Random Test Pattern generation method suitable for memory device verification. Failure conditions and failing pattern must be transferred to simulation for root-cause understanding, which is not directly possible due to the large gap between pattern length on ATE in the order of 106 clock cycles and pattern length limitations in simulation of 103 clock cycles. We present an extraction algorithm on ATE with DUT in the loop to extract the minimum length failing test pattern sequence for simulation and root-cause analysis. An application example is presented, weare a large Random Test Pattern revealed a special command sequence leading to device failure and how this sequence has been extracted for simulation. The presented random methods lead to fast detection of device issues by exploring the full coverage space. With the presented automated extraction that replaces manual interactive analysis, fast root-cause understanding with engineering time and ATE test-time reduction from typically few days to below one hour are achievable.