TY - GEN
T1 - Efficient Fault Injection for Embedded Systems
T2 - 24th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2018
AU - Maier, Petra R.
AU - Sharif, Uzair
AU - Mueller-Gritschneder, Daniel
AU - Schlichtmann, Ulf
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/9/26
Y1 - 2018/9/26
N2 - When used for safety-critical applications, embedded systems must behave safely at all times - even in the presence of random hardware faults. To ensure this, fault effect simulation by simulation-based fault injection is an integral part of embedded system development. The high complexity of embedded systems results in low simulation performance if all details of the system are simulated. Not simulating all details, i.e. increasing the simulation abstraction level, speeds up fault injection but can result in less accuracy in predicting the fault impacts on the system behavior. To achieve high accuracy and high simulation performance at the same time, we avoid simulation of details unrelated to the injected fault. For this, we divide the set of faults that can occur in an embedded system into three subsets. For each subset, we select the fault injection abstraction level of the embedded processor model that is as accurate as necessary but as fast as possible. The considered levels are host-compiled simulation, instruction set simulation and register transfer level simulation. For additional speed-up, the abstraction level can be switched during the fault injection simulation between register transfer and instruction set level. The fault set for host-compiled simulation can be reduced by static program analysis. Our results show that adapting the abstraction level to the fault set achieves high performance of the fault injection simulation.
AB - When used for safety-critical applications, embedded systems must behave safely at all times - even in the presence of random hardware faults. To ensure this, fault effect simulation by simulation-based fault injection is an integral part of embedded system development. The high complexity of embedded systems results in low simulation performance if all details of the system are simulated. Not simulating all details, i.e. increasing the simulation abstraction level, speeds up fault injection but can result in less accuracy in predicting the fault impacts on the system behavior. To achieve high accuracy and high simulation performance at the same time, we avoid simulation of details unrelated to the injected fault. For this, we divide the set of faults that can occur in an embedded system into three subsets. For each subset, we select the fault injection abstraction level of the embedded processor model that is as accurate as necessary but as fast as possible. The considered levels are host-compiled simulation, instruction set simulation and register transfer level simulation. For additional speed-up, the abstraction level can be switched during the fault injection simulation between register transfer and instruction set level. The fault set for host-compiled simulation can be reduced by static program analysis. Our results show that adapting the abstraction level to the fault set achieves high performance of the fault injection simulation.
KW - Fault injection
KW - abstraction level
KW - fault effect simulation
KW - host-compiled simulation
KW - instruction set simulation
KW - register transfer level
UR - http://www.scopus.com/inward/record.url?scp=85055855803&partnerID=8YFLogxK
U2 - 10.1109/IOLTS.2018.8474079
DO - 10.1109/IOLTS.2018.8474079
M3 - Conference contribution
AN - SCOPUS:85055855803
T3 - 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018
SP - 119
EP - 122
BT - 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018
A2 - Maniatakos, Mihalis
A2 - Alexandrescu, Dan
A2 - Gizopoulos, Dimitris
A2 - Papavramidou, Panagiota
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 2 July 2018 through 4 July 2018
ER -