Efficient event processing through reconfigurable hardware for algorithmic trading

Mohammad Sadoghi; Martin Labrecque; Harsh Singh; Warren Shum; Hans Arno Jacobsen

doi:10.14778/1920841.1921029

Efficient event processing through reconfigurable hardware for algorithmic trading

Mohammad Sadoghi, Martin Labrecque, Harsh Singh, Warren Shum, Hans Arno Jacobsen

University of Toronto

Research output: Contribution to journal › Article › peer-review

49 Scopus citations

Abstract

In this demo, we present fpga-ToPSS (Toronto Publish/Subscribe System Family), an efficient event processing platform for highfrequency and low-latency algorithmic trading. Our event processing platform is built over reconfigurable hardware-FPGAs-to achieve line-rate processing. Furthermore, our event processing engine supports Boolean expression matching with an expressive predicate language that models complex financial strategies to autonomously buy and sell stocks based on real-time financial data.

Original language	English
Pages (from-to)	1525-1528
Number of pages	4
Journal	Proceedings of the VLDB Endowment
Volume	3
Issue number	2
DOIs	https://doi.org/10.14778/1920841.1921029
State	Published - Sep 2010
Externally published	Yes

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abstract = "In this demo, we present fpga-ToPSS (Toronto Publish/Subscribe System Family), an efficient event processing platform for highfrequency and low-latency algorithmic trading. Our event processing platform is built over reconfigurable hardware-FPGAs-to achieve line-rate processing. Furthermore, our event processing engine supports Boolean expression matching with an expressive predicate language that models complex financial strategies to autonomously buy and sell stocks based on real-time financial data.",

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Efficient event processing through reconfigurable hardware for algorithmic trading

Abstract

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