Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources

Michael Feilen; Matthias Ihmig; Christian Schwarzbauer; Walter Stechele

doi:10.1109/FPL.2012.6339244

Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources

Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele

Default

Technical University of Munich

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

Demodulation and decoding of second generation terrestrial digital video broadcasting (DVB-T2) signals on general purpose processor platforms is challenging in terms of complexity and in terms of power. FPGA-based runtime acceleration for DVB-T2 allows for unwrapping the iterative structures of modern channel decoding schemes by using parallel hardware designs. Additionally, due to the sequential nature of the DVB-T2 receiver chain we can use partial reconfiguration to switch between different decoding modules. We will show in a theoretical analysis that this time-multiplexing approach can be used to realize resource-efficient DVB-T2 receiver chains at a much lower resource and power consumption as compared to solely processor-based solutions.

Original language	English
Title of host publication	Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Pages	75-82
Number of pages	8
DOIs	https://doi.org/10.1109/FPL.2012.6339244
State	Published - 2012
Event	22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway Duration: 29 Aug 2012 → 31 Aug 2012

Publication series

Name	Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Conference

Conference	22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Country/Territory	Norway
City	Oslo
Period	29/08/12 → 31/08/12

Access to Document

10.1109/FPL.2012.6339244

Cite this

Feilen, M., Ihmig, M., Schwarzbauer, C., & Stechele, W. (2012). Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 (pp. 75-82). Article 6339244 (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012). https://doi.org/10.1109/FPL.2012.6339244

@inproceedings{146702eb4fa240cc887da4a80796ed4b,

title = "Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources",

abstract = "Demodulation and decoding of second generation terrestrial digital video broadcasting (DVB-T2) signals on general purpose processor platforms is challenging in terms of complexity and in terms of power. FPGA-based runtime acceleration for DVB-T2 allows for unwrapping the iterative structures of modern channel decoding schemes by using parallel hardware designs. Additionally, due to the sequential nature of the DVB-T2 receiver chain we can use partial reconfiguration to switch between different decoding modules. We will show in a theoretical analysis that this time-multiplexing approach can be used to realize resource-efficient DVB-T2 receiver chains at a much lower resource and power consumption as compared to solely processor-based solutions.",

author = "Michael Feilen and Matthias Ihmig and Christian Schwarzbauer and Walter Stechele",

year = "2012",

doi = "10.1109/FPL.2012.6339244",

language = "English",

isbn = "9781467322560",

series = "Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012",

pages = "75--82",

booktitle = "Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012",

note = "22nd International Conference on Field Programmable Logic and Applications, FPL 2012 ; Conference date: 29-08-2012 Through 31-08-2012",

}

Feilen, M, Ihmig, M, Schwarzbauer, C & Stechele, W 2012, Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. in Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012., 6339244, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, pp. 75-82, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, 29/08/12. https://doi.org/10.1109/FPL.2012.6339244

Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. / Feilen, Michael; Ihmig, Matthias; Schwarzbauer, Christian et al.
Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 75-82 6339244 (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources

AU - Feilen, Michael

AU - Ihmig, Matthias

AU - Schwarzbauer, Christian

AU - Stechele, Walter

PY - 2012

Y1 - 2012

N2 - Demodulation and decoding of second generation terrestrial digital video broadcasting (DVB-T2) signals on general purpose processor platforms is challenging in terms of complexity and in terms of power. FPGA-based runtime acceleration for DVB-T2 allows for unwrapping the iterative structures of modern channel decoding schemes by using parallel hardware designs. Additionally, due to the sequential nature of the DVB-T2 receiver chain we can use partial reconfiguration to switch between different decoding modules. We will show in a theoretical analysis that this time-multiplexing approach can be used to realize resource-efficient DVB-T2 receiver chains at a much lower resource and power consumption as compared to solely processor-based solutions.

AB - Demodulation and decoding of second generation terrestrial digital video broadcasting (DVB-T2) signals on general purpose processor platforms is challenging in terms of complexity and in terms of power. FPGA-based runtime acceleration for DVB-T2 allows for unwrapping the iterative structures of modern channel decoding schemes by using parallel hardware designs. Additionally, due to the sequential nature of the DVB-T2 receiver chain we can use partial reconfiguration to switch between different decoding modules. We will show in a theoretical analysis that this time-multiplexing approach can be used to realize resource-efficient DVB-T2 receiver chains at a much lower resource and power consumption as compared to solely processor-based solutions.

UR - http://www.scopus.com/inward/record.url?scp=84870681341&partnerID=8YFLogxK

U2 - 10.1109/FPL.2012.6339244

DO - 10.1109/FPL.2012.6339244

M3 - Conference contribution

AN - SCOPUS:84870681341

SN - 9781467322560

T3 - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

SP - 75

EP - 82

BT - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

T2 - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Y2 - 29 August 2012 through 31 August 2012

ER -

Feilen M, Ihmig M, Schwarzbauer C, Stechele W. Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 75-82. 6339244. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012). doi: 10.1109/FPL.2012.6339244

Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this