Efficiency of body biasing in 90 nm CMOS for low power digital circuits

Klaus Von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

This paper presents an evaluation of body biasing based on measured static and dynamic device performance. The efficiency of body biasing in sub-130 nm CMOS circuits strongly depends on the device type and operating temperature. While forward biasing still provides a significant performance gain in a 90 nm CMOS triple well process, the efficiency of reverse biasing nearly vanishes. The impact of the zero temperature coefficient point on low voltage digital circuit design is investigated.

Original languageEnglish
Title of host publicationESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
EditorsM. Steyaert, C.L. Claeys
Pages175-178
Number of pages4
StatePublished - 2004
Externally publishedYes
EventESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference - Leuven, Belgium
Duration: 21 Sep 200423 Sep 2004

Publication series

NameESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Conference

ConferenceESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
Country/TerritoryBelgium
CityLeuven
Period21/09/0423/09/04

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