TY - GEN
T1 - Economic viability of hardware overprovisioning in power-constrained high performance computing
AU - Patki, Tapasya
AU - Lowenthal, David K.
AU - Rountree, Barry L.
AU - Schulz, Martin
AU - Supinski, Bronis R.De
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2017/1/23
Y1 - 2017/1/23
N2 - Recent research has established that hardware overprovisioning can improve system power utilization as well as job throughput in power-constrained, high-performance computing environments significantly. These benefits, however, may be associated with an additional infrastructure cost, making hardware overprovisioned systems less viable economically. It is thus important to conduct a detailed cost-benefit analysis before investing in such systems at a large-scale. In this paper, we develop a model to conduct this analysis and show that for a given, fixed infrastructure cost budget and a system power budget, it is possible for hardware overprovisioned systems to lead to a net performance benefit when compared to traditional, worst-case provisioned HPC systems.
AB - Recent research has established that hardware overprovisioning can improve system power utilization as well as job throughput in power-constrained, high-performance computing environments significantly. These benefits, however, may be associated with an additional infrastructure cost, making hardware overprovisioned systems less viable economically. It is thus important to conduct a detailed cost-benefit analysis before investing in such systems at a large-scale. In this paper, we develop a model to conduct this analysis and show that for a given, fixed infrastructure cost budget and a system power budget, it is possible for hardware overprovisioned systems to lead to a net performance benefit when compared to traditional, worst-case provisioned HPC systems.
UR - https://www.scopus.com/pages/publications/85013957188
U2 - 10.1109/E2SC.2016.007
DO - 10.1109/E2SC.2016.007
M3 - Conference contribution
AN - SCOPUS:85013957188
T3 - Proceedings of E2SC 2016: 4th International Workshop on Energy Efficient Supercomputing - Held in conjunction with SC 2016: The International Conference for High Performance Computing, Networking, Storage and Analysis
SP - 8
EP - 15
BT - Proceedings of E2SC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th International Workshop on Energy Efficient Supercomputing, E2SC 2016 Held in conjunction with The International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2016
Y2 - 13 November 2016 through 18 November 2016
ER -