Dynamic state-retention FlipFlop for fine-grained sleep-transistor scheme

Stephan Henzler; Thomas Nirschl; Christian Pacha; Peter Spindler; Philip Teichmann; Michael Fulde; Juergen Fischer; Matthias Eireiner; Thomas Fischer; Georg Georgakos; Joerg Berthold; Doris Schmitt-Landsiedel

doi:10.1109/ESSCIR.2005.1541580

Dynamic state-retention FlipFlop for fine-grained sleep-transistor scheme

Stephan Henzler
, Thomas Nirschl
, Christian Pacha
, Peter Spindler
, Philip Teichmann
, Michael Fulde
, Juergen Fischer
, Matthias Eireiner
, Thomas Fischer
, Georg Georgakos
, Joerg Berthold
, Doris Schmitt-Landsiedel

Medicine and Health

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Fine-grained sleep transistor scheme is the rigorous application of power gating to reduce standby power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense amplifier based state retention flip-flop preserving the logical state of the circuit during this short idle times is proposed, that requires neither additional control signals nor an additional power supply for it's state retention functionality and can be integrated into a standard design flow without any modifications. The trade-off between propagation delay and retention time is derived analytically. Retention times in the range of milli-seconds can be achieved with D-to-Q delays of 100ps to 200ps.

Original language	English
Title of host publication	Proceedings of ESSCIRC 2005
Subtitle of host publication	31st European Solid-State Circuits Conference
Pages	145-148
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIR.2005.1541580
State	Published - 2005
Event	ESSCIRC 2005: 31st European Solid-State Circuits Conference - Grenoble, France Duration: 12 Sep 2005 → 16 Sep 2005

Publication series

Name	Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Conference

Conference	ESSCIRC 2005: 31st European Solid-State Circuits Conference
Country/Territory	France
City	Grenoble
Period	12/09/05 → 16/09/05

Access to Document

10.1109/ESSCIR.2005.1541580

Cite this

Henzler, S., Nirschl, T., Pacha, C., Spindler, P., Teichmann, P., Fulde, M., Fischer, J., Eireiner, M., Fischer, T., Georgakos, G., Berthold, J., & Schmitt-Landsiedel, D. (2005). Dynamic state-retention FlipFlop for fine-grained sleep-transistor scheme. In Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference (pp. 145-148). Article 1541580 (Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIR.2005.1541580

@inproceedings{f43ef6f98c384cdfb7ea5dcb8b99e987,

title = "Dynamic state-retention FlipFlop for fine-grained sleep-transistor scheme",

abstract = "Fine-grained sleep transistor scheme is the rigorous application of power gating to reduce standby power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense amplifier based state retention flip-flop preserving the logical state of the circuit during this short idle times is proposed, that requires neither additional control signals nor an additional power supply for it's state retention functionality and can be integrated into a standard design flow without any modifications. The trade-off between propagation delay and retention time is derived analytically. Retention times in the range of milli-seconds can be achieved with D-to-Q delays of 100ps to 200ps.",

author = "Stephan Henzler and Thomas Nirschl and Christian Pacha and Peter Spindler and Philip Teichmann and Michael Fulde and Juergen Fischer and Matthias Eireiner and Thomas Fischer and Georg Georgakos and Joerg Berthold and Doris Schmitt-Landsiedel",

year = "2005",

doi = "10.1109/ESSCIR.2005.1541580",

language = "English",

isbn = "0780392051",

series = "Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference",

pages = "145--148",

booktitle = "Proceedings of ESSCIRC 2005",

note = "ESSCIRC 2005: 31st European Solid-State Circuits Conference ; Conference date: 12-09-2005 Through 16-09-2005",

}

Henzler, S, Nirschl, T, Pacha, C, Spindler, P, Teichmann, P, Fulde, M, Fischer, J, Eireiner, M, Fischer, T, Georgakos, G, Berthold, J & Schmitt-Landsiedel, D 2005, Dynamic state-retention FlipFlop for fine-grained sleep-transistor scheme. in Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference., 1541580, Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference, pp. 145-148, ESSCIRC 2005: 31st European Solid-State Circuits Conference, Grenoble, France, 12/09/05. https://doi.org/10.1109/ESSCIR.2005.1541580

Dynamic state-retention FlipFlop for fine-grained sleep-transistor scheme. / Henzler, Stephan; Nirschl, Thomas; Pacha, Christian et al.
Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference. 2005. p. 145-148 1541580 (Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Henzler, Stephan

AU - Nirschl, Thomas

AU - Pacha, Christian

AU - Spindler, Peter

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AU - Fulde, Michael

AU - Fischer, Juergen

AU - Eireiner, Matthias

AU - Fischer, Thomas

AU - Georgakos, Georg

AU - Berthold, Joerg

AU - Schmitt-Landsiedel, Doris

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N2 - Fine-grained sleep transistor scheme is the rigorous application of power gating to reduce standby power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense amplifier based state retention flip-flop preserving the logical state of the circuit during this short idle times is proposed, that requires neither additional control signals nor an additional power supply for it's state retention functionality and can be integrated into a standard design flow without any modifications. The trade-off between propagation delay and retention time is derived analytically. Retention times in the range of milli-seconds can be achieved with D-to-Q delays of 100ps to 200ps.

AB - Fine-grained sleep transistor scheme is the rigorous application of power gating to reduce standby power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense amplifier based state retention flip-flop preserving the logical state of the circuit during this short idle times is proposed, that requires neither additional control signals nor an additional power supply for it's state retention functionality and can be integrated into a standard design flow without any modifications. The trade-off between propagation delay and retention time is derived analytically. Retention times in the range of milli-seconds can be achieved with D-to-Q delays of 100ps to 200ps.

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ER -

Dynamic state-retention FlipFlop for fine-grained sleep-transistor scheme

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