Duty cycles in digital logic applications: A realistic way of considering hot-carrier reliability

W. Weber; M. Brox; T. Kunemund; D. Schmitt-Landsiedel; Q. Wang

Duty cycles in digital logic applications: A realistic way of considering hot-carrier reliability

W. Weber, M. Brox, T. Kunemund, D. Schmitt-Landsiedel, Q. Wang

Siemens AG

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper various stages as appearing in digital logic, like inverters, NANDs, NORs, and transfer gates are hot-carrier stressed. Transient effects and the one of voltage combinations are discussed and an estimation for a realistic lifetime criterion is given.

Original language	English
Title of host publication	ESSDERC 1990 - 20th European Solid State Device Research Conference
Editors	W. Eccleston, P. J. Rosser
Publisher	IEEE Computer Society
Pages	291-294
Number of pages	4
ISBN (Electronic)	0750300655
State	Published - 1990
Externally published	Yes
Event	20th European Solid State Device Research Conference, ESSDERC 1990 - Nottingham, United Kingdom Duration: 10 Sep 1990 → 13 Sep 1990

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Conference

Conference	20th European Solid State Device Research Conference, ESSDERC 1990
Country/Territory	United Kingdom
City	Nottingham
Period	10/09/90 → 13/09/90

Cite this

Weber, W., Brox, M., Kunemund, T., Schmitt-Landsiedel, D., & Wang, Q. (1990). Duty cycles in digital logic applications: A realistic way of considering hot-carrier reliability. In W. Eccleston, & P. J. Rosser (Eds.), ESSDERC 1990 - 20th European Solid State Device Research Conference (pp. 291-294). Article 5436356 (European Solid-State Device Research Conference). IEEE Computer Society.

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title = "Duty cycles in digital logic applications: A realistic way of considering hot-carrier reliability",

abstract = "In this paper various stages as appearing in digital logic, like inverters, NANDs, NORs, and transfer gates are hot-carrier stressed. Transient effects and the one of voltage combinations are discussed and an estimation for a realistic lifetime criterion is given.",

author = "W. Weber and M. Brox and T. Kunemund and D. Schmitt-Landsiedel and Q. Wang",

note = "Publisher Copyright: {\textcopyright} 1990 IOP Publishing Ltd.; 20th European Solid State Device Research Conference, ESSDERC 1990 ; Conference date: 10-09-1990 Through 13-09-1990",

year = "1990",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "IEEE Computer Society",

pages = "291--294",

editor = "W. Eccleston and Rosser, {P. J.}",

booktitle = "ESSDERC 1990 - 20th European Solid State Device Research Conference",

}

Weber, W, Brox, M, Kunemund, T, Schmitt-Landsiedel, D & Wang, Q 1990, Duty cycles in digital logic applications: A realistic way of considering hot-carrier reliability. in W Eccleston & PJ Rosser (eds), ESSDERC 1990 - 20th European Solid State Device Research Conference., 5436356, European Solid-State Device Research Conference, IEEE Computer Society, pp. 291-294, 20th European Solid State Device Research Conference, ESSDERC 1990, Nottingham, United Kingdom, 10/09/90.

Duty cycles in digital logic applications: A realistic way of considering hot-carrier reliability. / Weber, W.; Brox, M.; Kunemund, T. et al.
ESSDERC 1990 - 20th European Solid State Device Research Conference. ed. / W. Eccleston; P. J. Rosser. IEEE Computer Society, 1990. p. 291-294 5436356 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Duty cycles in digital logic applications

T2 - 20th European Solid State Device Research Conference, ESSDERC 1990

AU - Weber, W.

AU - Brox, M.

AU - Kunemund, T.

AU - Schmitt-Landsiedel, D.

AU - Wang, Q.

PY - 1990

Y1 - 1990

N2 - In this paper various stages as appearing in digital logic, like inverters, NANDs, NORs, and transfer gates are hot-carrier stressed. Transient effects and the one of voltage combinations are discussed and an estimation for a realistic lifetime criterion is given.

AB - In this paper various stages as appearing in digital logic, like inverters, NANDs, NORs, and transfer gates are hot-carrier stressed. Transient effects and the one of voltage combinations are discussed and an estimation for a realistic lifetime criterion is given.

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M3 - Conference contribution

AN - SCOPUS:84907980395

T3 - European Solid-State Device Research Conference

SP - 291

EP - 294

BT - ESSDERC 1990 - 20th European Solid State Device Research Conference

A2 - Eccleston, W.

A2 - Rosser, P. J.

PB - IEEE Computer Society

Y2 - 10 September 1990 through 13 September 1990

ER -

Duty cycles in digital logic applications: A realistic way of considering hot-carrier reliability

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