Dual supply voltage scaling in a conventional power-driven logic synthesis environment

Torsten Mahnke; Walter Stechele; Wolfgang Hoeld

doi:10.1007/3-540-45716-x_15

Dual supply voltage scaling in a conventional power-driven logic synthesis environment

Torsten Mahnke
, Walter Stechele
, Wolfgang Hoeld

Chair of Integrated Systems

Technical University of Munich
National Semiconductor GmbH

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.

Original language	English
Title of host publication	Integrated Circuit Design
Subtitle of host publication	Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings
Editors	Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
Publisher	Springer Verlag
Pages	146-155
Number of pages	10
ISBN (Print)	9783540441434
DOIs	https://doi.org/10.1007/3-540-45716-x_15
State	Published - 2002
Event	12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 - Seville, Spain Duration: 11 Sep 2002 → 13 Sep 2002

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	2451
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002
Country/Territory	Spain
City	Seville
Period	11/09/02 → 13/09/02

Access to Document

10.1007/3-540-45716-x_15

Cite this

Mahnke, T., Stechele, W., & Hoeld, W. (2002). Dual supply voltage scaling in a conventional power-driven logic synthesis environment. In B. Hochet, A. J. Acosta, & M. J. Bellido (Eds.), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings (pp. 146-155). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2451). Springer Verlag. https://doi.org/10.1007/3-540-45716-x_15

Mahnke, Torsten ; Stechele, Walter ; Hoeld, Wolfgang. / Dual supply voltage scaling in a conventional power-driven logic synthesis environment. Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. editor / Bertrand Hochet ; Antonio J. Acosta ; Manuel J. Bellido. Springer Verlag, 2002. pp. 146-155 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{b2bcca424d9e4bf5af4aa2cb0d1488b1,

title = "Dual supply voltage scaling in a conventional power-driven logic synthesis environment",

abstract = "Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10\% on average and 24\% in the best case have been achieved.",

author = "Torsten Mahnke and Walter Stechele and Wolfgang Hoeld",

note = "Publisher Copyright: {\textcopyright} Springer-Verlag Berlin Heidelberg 2002.; 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 ; Conference date: 11-09-2002 Through 13-09-2002",

year = "2002",

doi = "10.1007/3-540-45716-x\_15",

language = "English",

isbn = "9783540441434",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "146--155",

editor = "Bertrand Hochet and Acosta, \{Antonio J.\} and Bellido, \{Manuel J.\}",

booktitle = "Integrated Circuit Design",

}

Mahnke, T, Stechele, W & Hoeld, W 2002, Dual supply voltage scaling in a conventional power-driven logic synthesis environment. in B Hochet, AJ Acosta & MJ Bellido (eds), Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 2451, Springer Verlag, pp. 146-155, 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, Seville, Spain, 11/09/02. https://doi.org/10.1007/3-540-45716-x_15

Dual supply voltage scaling in a conventional power-driven logic synthesis environment. / Mahnke, Torsten; Stechele, Walter; Hoeld, Wolfgang.
Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. ed. / Bertrand Hochet; Antonio J. Acosta; Manuel J. Bellido. Springer Verlag, 2002. p. 146-155 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2451).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Dual supply voltage scaling in a conventional power-driven logic synthesis environment

AU - Mahnke, Torsten

AU - Stechele, Walter

AU - Hoeld, Wolfgang

N1 - Publisher Copyright: © Springer-Verlag Berlin Heidelberg 2002.

PY - 2002

Y1 - 2002

N2 - Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.

AB - Dual supply voltage scaling (DSVS) is an emerging technique in logic-level power optimization. In this paper, a novel design methodology, which enables DSVS to be carried out in a state-of-the-art environment for power-driven logic synthesis, is presented. The idea is to provide a dual supply voltage standard cell library modeled such that a typical gate sizing algorithm can be exploited for DSVS. Since this approach renders dedicated DSVS algorithms superfluous, only little modification of established design flows is required. The methodology has been applied to MCNC benchmark circuits. Compared to the results of single supply voltage power-driven logic synthesis, additional power reductions of 10% on average and 24% in the best case have been achieved.

UR - https://www.scopus.com/pages/publications/84943259642

U2 - 10.1007/3-540-45716-x_15

DO - 10.1007/3-540-45716-x_15

M3 - Conference contribution

AN - SCOPUS:84943259642

SN - 9783540441434

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 146

EP - 155

BT - Integrated Circuit Design

A2 - Hochet, Bertrand

A2 - Acosta, Antonio J.

A2 - Bellido, Manuel J.

PB - Springer Verlag

T2 - 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002

Y2 - 11 September 2002 through 13 September 2002

ER -

Mahnke T, Stechele W, Hoeld W. Dual supply voltage scaling in a conventional power-driven logic synthesis environment. In Hochet B, Acosta AJ, Bellido MJ, editors, Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation - 12th International Workshop, PATMOS 2002, Proceedings. Springer Verlag. 2002. p. 146-155. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-45716-x_15

Dual supply voltage scaling in a conventional power-driven logic synthesis environment

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