Distributed hardware-in-the-loop satellite simulation architecture for creating “Digital Shadows” of Satellite Constellations

We propose a modular hardware in the loop architecture for simulating space system operations including satellite simulations, flatsat data, and satellites flying in orbit. This approach aims at creating a digital shadow for assessing potential evolutions of satellite constellations and improve the fidelity of management of contingency scenarios. Our simulation architecture allows for quick assessment of alternatives and on-the-ground verification of satellites together with hardware-in-the-loop setups, where physical sensor input is impossible due to the different environment. Utilising software based on the IEEE 1516-2010 Standard for Modeling and Simulation (M&S) High Level Architecture (HLA), we combine several simulations of satellite and satellite subsystems with hardware components. Compared to existing simulation environments, simulations of several domains can be combined easily and run together with hardware components, while placing fewer limits on the number of simulations running together. On that basis we examine the communication chain from simulator to orbit, to present a model for a hardware-in-the-loop simulator architecture that can include systems currently in orbit, like pilot-in-the-loop systems which are common in aeronautical simulations. We then compare advantages and disadvantages and discuss the real-time capabilities of the system, considering nanosatellite systems. As a use case, we simulate the detection of objects by a satellite constellation, using a neuromorphic camera. A reconfigurable simulation environment allows to assess this potential in the early project stages by quickly evaluating different scenarios in higher detail than previous research, which is mainly based on simple models for each stage. This paper describes the system architecture of our hardware-in-the-loop simulator and illustrates the initial results of our software implementation, based on the integration of single board computers as interface and computing nodes.