Diagnosis-aware system design for automotive E/E architectures

Peter Waszecki, Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


This paper proposes a schedule synthesis approach taking fault diagnosis and testability into account at design time. Over the last years, the amount of automotive software and hardware has been successively growing. As a consequence, the complexity of present-day Electrical and Electronic (E/E) architectures reached a state where current fault detection mechanisms are often not sufficient or computationally too expensive to guarantee a reliable system functionality. As a remedy, we propose a novel design methodology, optimizing a subsequent fault diagnosis in terms of the necessary detection time as well as the diagnostic resolution. Our approach is based on a time-triggered architecture and aims at a decentralized message-based fault diagnosis solution. In order to increase the system reliability, during schedule synthesis a modified and adapted message distribution is taken into account which additionally considers previously undiagnosable resources. While our approach might lead to a slightly increased bandwidth utilization, it clearly improves the overall diagnosis of faulty resources by a reduced detection time and an increased diagnostic resolution.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781479948338
StatePublished - 2 Feb 2015
Event14th International Symposium on Integrated Circuits, ISIC 2014 - Singapore, Singapore
Duration: 10 Dec 201412 Dec 2014

Publication series

NameProceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014


Conference14th International Symposium on Integrated Circuits, ISIC 2014


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