Device level based cell modeling for fast power estimation

Christian V. Schimpfle, Sven Simon, Josef A. Nossek

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this work, a method for fast power estimation in complex digital circuits is presented. Properties like delay and power consumption of a circuits basic cells are extracted precisely by circuit level simulations. The cell model then includes delay and power consumption values for all possible transitions at the cell inputs. The total power consumption is finally determined by logic simulation at higher architectural levels. The cell model also includes the glitching behavior at the outputs resulting from different path delays inside a cell. It is shown experimentally that this delay model, including glitches generated by the basic cells, leads to good power estimation results of complex circuits within an accuracy of 8% in the worst case and needs 4 and 2 orders of magnitude less simulation time than SPICE and PowerMill respectively.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
PagesI-90 - I-93
ISBN (Print)0780354729
StatePublished - 1999
EventProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
Duration: 30 May 19992 Jun 1999

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume1
ISSN (Print)0271-4310

Conference

ConferenceProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
CityOrlando, FL, USA
Period30/05/992/06/99

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