Abstract
Performance space exploration (PSE) determines the range of feasible performance values of a circuit block for a given topology and technology. In this paper, we present two deterministic approaches for PSE. One approximates the feasible performance space based on linearized circuit models and is suitable for investigating a large number of performances. The other one computes discretizations of the Pareto front of competing performances. In addition, a motivation and application of PSE using a hierarchical design example is presented.
| Original language | English |
|---|---|
| Article number | 51.1 |
| Pages (from-to) | 869-874 |
| Number of pages | 6 |
| Journal | Proceedings - Design Automation Conference |
| DOIs | |
| State | Published - 2005 |
| Event | 42nd Design Automation Conference, DAC 2005 - Anaheim, CA, United States Duration: 13 Jun 2005 → 17 Jun 2005 |
Keywords
- Analog Integrated Circuits
- Fourier Motzkin Elimination
- Pareto Optimization
- Performance Space Exploration
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