Deterministic analog placement by enhanced shape functions

For analog integrated circuits, generating a layout represents the bottleneck in the design flow. To automate the layout step, it is necessary to create placements with respect to various constraints automatically. Since the constraints can be numerous, an automatic generation of the layout constraints is crucial as well. In this chapter, a comprehensive and deterministic methodology for analog layout design automation is presented. An approach to automatically generate constraints for analog circuits is described. It recognizes building blocks, e.g., current mirrors, and symmetry conditions in the circuit and, with prioritized rules, generates constraints and hierarchy information. Then, a placement algorithm, called Plantage, is presented, which is capable to handle all relevant constraints. It uses the hierarchy information of the previous step to guide an enumeration process. Plantage calculates a Pareto front of placements with respect to different aspect ratios. The results show high quality in terms of area and postlayout circuit performance.