Design verification considering manufacturing tolerances by using worst-case distances

In this paper, a new method for design verification on circuit level considering the inevitable manufacturing tolerances is presented. It is based on a specific backward evaluation of performance specifications, which can be done efficiently with a sequential quadratic programming method using standard simulation tools. The specific backward evaluation yields exact worst-case parameter sets and corresponding worst-case distances for all specifications separately. They form the basis of an automatic circuit quality analysis considering performance and robustness, that includes an accurate yield estimation at no additional circuit simulation costs. The automatic circuit quality analysis enables a detailed design verification and supports the circuit design process by planning aids for a design step. The various features of the method will be illustrated using a small tutorial circuit example. A practical example of an integrated CMOS analog circuit will prove the efficiency of the new approach.