Design of ultra-low-power arithmetic structures in adiabatic logic

Due to increasing range and sophistication of battery-operated applications and rising power densities due to shrinking, low-power design has become a main issue in modern CMOS technologies. One way to reduce the dissipated energy is to apply a circuit style known as adiabatic logic, that operates most efficient at moderate frequencies around 100MHz and saves more than 80% of the energy compared to static CMOS, in an industrial 130nm CMOS process. Nevertheless, on system level some inherent properties of adiabtic logic have to be taken into account to design ultra-low-power systems. In this work, arithmetic building blocks in adiabatic circuit design style are investigated. The saving factor gained on system level is limited by the efficiency in the generation of the multi-phase clock applied to energy-efficient adiabatic logic families like the Positive Feedback Adiabatic Logic PFAL. On the one hand, this efficiency is limited by the topology of the 4-phase oscillator used for the operation of PFAL and on the other hand, the quality factor of integrated coils has a major impact on the efficiency as well. As demonstrator for the applicability of adiabatic logic for ultra-low-power arithmetic systems a Discrete-Cosine Transformation DCT is used in this work.