Design of a Low Multi-Loop Inductance Three Level Neutral Point Clamped Inverter with GaN HEMTs

Keyphrases

• Printed Circuit Board 100%
• Neutral Point Clamped Three-level Inverter (NPCTLI) 100%
• Neutral-point Clamped 100%
• Loop Inductance 100%
• Capacitive Coupling 100%
• GaN HEMT 100%
• Multi-loop 100%
• Performance Improvement 50%
• Dielectric Materials 50%
• Numerical Analysis 50%
• Inductive Coupling 50%
• Printed Circuits 50%
• Ultra-low 50%
• Polyimide 50%
• Cell Design 50%
• Switching Performance 50%
• Three-level Inverter 50%
• Clamp Cell 50%
• Gated Resistor 50%
• Low Inductance 50%
• Printed Circuit Board Design 50%
• Parasitic Inductance 50%
• Commutation Loop Inductance 50%
• Commutation Loop 50%
• Switching Cell 50%
• Prepreg 50%
• Board Thickness 50%
• Bare Die 50%
• Voltage Overshoot 50%
• Switching Test 50%
• Maximum Voltage 50%
• Interlayer Dielectric 50%

Engineering

• Neutral Point 100%
• Printed Circuit Board 100%
• Inverter 100%
• Capacitive Coupling 66%
• Dielectrics 33%
• Performance Improvement 33%
• Inductive Coupling 33%
• Cell Design 33%
• Experimental Measurement 33%
• Interlayer 33%
• Printed Circuit 33%