Abstract
We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. We describe the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. We quantify our approach with a performance evaluation of the overall system.
| Original language | English |
|---|---|
| Pages (from-to) | 623-640 |
| Number of pages | 18 |
| Journal | Computer Networks |
| Volume | 41 |
| Issue number | 5 |
| DOIs | |
| State | Published - 5 Apr 2003 |
| Externally published | Yes |
Keywords
- Modular and scalable architectures
- Network processors
- Open systems
- Performance evaluation
- Systems on a chip
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