Design methodology for a large communication chip

Rolf Clauberg; Peter Buchmann; Andreas Herkersdorf; David J. Webb

doi:10.1109/54.867899

Design methodology for a large communication chip

Rolf Clauberg, Peter Buchmann, Andreas Herkersdorf, David J. Webb

Chair of Integrated Systems

IBM Zurich Research Laboratory

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

Smart chip is a large communication chip with standard-based communication interfaces, multiple clock domains, and mixed-signal components for line interfacing. This chip has been developed by focusing mainly on general design aspects.

Original language	English
Pages (from-to)	86-94
Number of pages	9
Journal	IEEE Design and Test of Computers
Volume	17
Issue number	3
DOIs	https://doi.org/10.1109/54.867899
State	Published - Jul 2000

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Design methodology for a large communication chip

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