TY - GEN
T1 - Design Cube - a model for VHDL designflow representation
AU - Ecker, W.
AU - Hofmeister, M.
PY - 1992
Y1 - 1992
N2 - Hardware design under the use of the hardware description language VHDL has to consider three independent property scales that influence the design process from an abstract level to gate level, namely the design view, the timing aspect, and the value representation. The well known Y-chart model is not suitable to describe these property scales in a satisfactory way; furthermore, this model contains the aspects of placement and routing, which are not supported by VHDL due to the fact that these steps are performed by conventional tools. In this paper, a new model for the design flow representation with the particular view on VHDL is presented.
AB - Hardware design under the use of the hardware description language VHDL has to consider three independent property scales that influence the design process from an abstract level to gate level, namely the design view, the timing aspect, and the value representation. The well known Y-chart model is not suitable to describe these property scales in a satisfactory way; furthermore, this model contains the aspects of placement and routing, which are not supported by VHDL due to the fact that these steps are performed by conventional tools. In this paper, a new model for the design flow representation with the particular view on VHDL is presented.
UR - https://www.scopus.com/pages/publications/0026963771
M3 - Conference contribution
AN - SCOPUS:0026963771
SN - 0818627808
T3 - European Design Automation Conference
SP - 752
EP - 757
BT - European Design Automation Conference
PB - Publ by IEEE
T2 - European Design Automation Conference -EURO-VHDL '92
Y2 - 7 September 1992 through 10 September 1992
ER -