TY - GEN
T1 - Design Close to the Edge for Advanced Technology using Machine Learning and Brain-Inspired Algorithms
AU - Amrouch, Hussam
AU - Klemme, Florian
AU - Genssler, Paul R.
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - In advanced technology nodes, transistor performance is increasingly impacted by different types of design-time and run-time degradation. First, variation is inherent to the manufacturing process and is constant over the lifetime. Second, aging effects degrade the transistor over its whole life and can cause failures later on. Both effects impact the underlying electrical properties of which the threshold voltage is the most important. To estimate the degradation-induced changes in the transistor performance for a whole circuit, extensive SPICE simulations have to be performed. However, for large circuits, the computational effort of such simulations can become infeasible very quickly. Furthermore, the SPICE simulations cannot be delegated to circuit designers, since the required underlying transistor models cannot be shared due to their high confidentiality for the foundry. In this paper, we tackle these challenges at multiple levels, ranging from transistor to memory to circuit level. We employ machine learning and brain-inspired algorithms to overcome computational infeasibility and confidentiality problems, paving the way towards design close to the edge.
AB - In advanced technology nodes, transistor performance is increasingly impacted by different types of design-time and run-time degradation. First, variation is inherent to the manufacturing process and is constant over the lifetime. Second, aging effects degrade the transistor over its whole life and can cause failures later on. Both effects impact the underlying electrical properties of which the threshold voltage is the most important. To estimate the degradation-induced changes in the transistor performance for a whole circuit, extensive SPICE simulations have to be performed. However, for large circuits, the computational effort of such simulations can become infeasible very quickly. Furthermore, the SPICE simulations cannot be delegated to circuit designers, since the required underlying transistor models cannot be shared due to their high confidentiality for the foundry. In this paper, we tackle these challenges at multiple levels, ranging from transistor to memory to circuit level. We employ machine learning and brain-inspired algorithms to overcome computational infeasibility and confidentiality problems, paving the way towards design close to the edge.
KW - Brain-Inspired Computing
KW - Cell Libraries
KW - FinFET
KW - ML-CAD
KW - Machine Learning
KW - Reliability
KW - SRAM
UR - http://www.scopus.com/inward/record.url?scp=85126095033&partnerID=8YFLogxK
U2 - 10.1109/ASP-DAC52403.2022.9712493
DO - 10.1109/ASP-DAC52403.2022.9712493
M3 - Conference contribution
AN - SCOPUS:85126095033
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 493
EP - 499
BT - ASP-DAC 2022 - 27th Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022
Y2 - 17 January 2022 through 20 January 2022
ER -