Design based failure analysis and yield improvement in CMOS-circuits

In this paper we show that defect simulation is a basis for yield enhancement strategies. These strategies involve identification of the yield detractors (i.e. identification of spot defect characteristics) and yield oriented layout design, which uses information about defects. Information about key yield detractors can be obtained in a time and cost efficient manner using defect simulation. By comparison of process variants and of SRAMs with different layouts, the sensitivity of the method for process changes as well as for design differences is illustrated. This leads to the conclusion that the defect and yield simulation tools can be used for yield oriented design. The enormous cost and time savings demonstrated in this work give a signal to enforce the introduction of design based failure simulation methods into the yield learning process.