TY - JOUR
T1 - Cryogenic Hyperdimensional In-Memory Computing Using Ferroelectric TCAM
AU - Singh Parihar, Shivendra
AU - Kumar, Shubham
AU - Chatterjee, Swetaki
AU - Pahwa, Girish
AU - Singh Chauhan, Yogesh
AU - Amrouch, Hussam
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2025
Y1 - 2025
N2 - Cryogenic operations of electronics present a significant step forward to achieve huge demand of in-memory computing (IMC) for high-performance computing, quantum computing, and military applications. Ferroelectric (FE) is a promising candidate to develop the complementary metal oxide semiconductor (CMOS)-compatible nonvolatile memories. Hence, in this work, we investigate the effectiveness of IMC using emerging FE technology at the 5-nm technology node. To achieve that, we begin by characterizing commercial 5-nm fin field-effect transistors (FinFETs) from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model [Berkeley Short-channel IGFET Model-Common Multi-Gate (BSIM-CMG)] to accurately reproduce the measurements. Afterward, we use the Preisach-model-based approach to incorporate the impact of FE within the BSIM-CMG model framework using the measurements from FE capacitor to realize ferroelectric fin field-effect transistors (Fe-FinFETs) operating from 300 down to 10 K. Then, as proof of concept, we focus on 1 × 8 ternary content addressable memory (TCAM) array that is used to perform language classification and voice recognition using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of TCAM-based IMC all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC. We reveal that cryogenic temperatures lead to the worst performance in Fe-FinFET-based TCAM. Hence, we have also proposed solutions to improve the cryogenic performance of Fe-FinFET-based TCAM.
AB - Cryogenic operations of electronics present a significant step forward to achieve huge demand of in-memory computing (IMC) for high-performance computing, quantum computing, and military applications. Ferroelectric (FE) is a promising candidate to develop the complementary metal oxide semiconductor (CMOS)-compatible nonvolatile memories. Hence, in this work, we investigate the effectiveness of IMC using emerging FE technology at the 5-nm technology node. To achieve that, we begin by characterizing commercial 5-nm fin field-effect transistors (FinFETs) from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model [Berkeley Short-channel IGFET Model-Common Multi-Gate (BSIM-CMG)] to accurately reproduce the measurements. Afterward, we use the Preisach-model-based approach to incorporate the impact of FE within the BSIM-CMG model framework using the measurements from FE capacitor to realize ferroelectric fin field-effect transistors (Fe-FinFETs) operating from 300 down to 10 K. Then, as proof of concept, we focus on 1 × 8 ternary content addressable memory (TCAM) array that is used to perform language classification and voice recognition using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of TCAM-based IMC all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC. We reveal that cryogenic temperatures lead to the worst performance in Fe-FinFET-based TCAM. Hence, we have also proposed solutions to improve the cryogenic performance of Fe-FinFET-based TCAM.
KW - 5-nm fin field-effect transistor (FinFET)
KW - compact modeling
KW - cryogenic complementary metal oxide semiconductor (CMOS)
KW - ferroelectric fin field-effect transistor (FeFinFET)
KW - hyperdimensional computing (HDC)
KW - in-memory computing (IMC)
UR - http://www.scopus.com/inward/record.url?scp=86000319837&partnerID=8YFLogxK
U2 - 10.1109/JXCDC.2025.3547797
DO - 10.1109/JXCDC.2025.3547797
M3 - Article
AN - SCOPUS:86000319837
SN - 2329-9231
VL - 11
SP - 34
EP - 41
JO - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
JF - IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
ER -