Critical area analysis for design‐based yield improvement of vlsi circuits

Doris Schmitt‐Landsiedel, Doris Keitel‐Schulz, Jitendra Khare, Susanne Griep, Wojciech Maly

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


Yield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated for design based yield prediction and improvement. Experimental results for a typical CMOS process are provided.

Original languageEnglish
Pages (from-to)227-232
Number of pages6
JournalQuality and Reliability Engineering International
Issue number4
StatePublished - 1995
Externally publishedYes


  • critical area
  • defect simulation
  • design‐based yield improvement
  • failure analysis
  • yield learning


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