Critical area analysis for design‐based yield improvement of vlsi circuits

Doris Schmitt‐Landsiedel; Doris Keitel‐Schulz; Jitendra Khare; Susanne Griep; Wojciech Maly

doi:10.1002/qre.4680110403

Critical area analysis for design‐based yield improvement of vlsi circuits

Doris Schmitt‐Landsiedel, Doris Keitel‐Schulz, Jitendra Khare, Susanne Griep, Wojciech Maly

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

Yield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated for design based yield prediction and improvement. Experimental results for a typical CMOS process are provided.

Original language	English
Pages (from-to)	227-232
Number of pages	6
Journal	Quality and Reliability Engineering International
Volume	11
Issue number	4
DOIs	https://doi.org/10.1002/qre.4680110403
State	Published - 1995
Externally published	Yes

Keywords

critical area
defect simulation
design‐based yield improvement
failure analysis
yield learning

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10.1002/qre.4680110403

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@article{e18f095ce43d4b0b8035cc1cef614627,

title = "Critical area analysis for design‐based yield improvement of vlsi circuits",

abstract = "Yield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated for design based yield prediction and improvement. Experimental results for a typical CMOS process are provided.",

keywords = "critical area, defect simulation, design‐based yield improvement, failure analysis, yield learning",

author = "Doris Schmitt‐Landsiedel and Doris Keitel‐Schulz and Jitendra Khare and Susanne Griep and Wojciech Maly",

year = "1995",

doi = "10.1002/qre.4680110403",

language = "English",

volume = "11",

pages = "227--232",

journal = "Quality and Reliability Engineering International",

issn = "0748-8017",

publisher = "John Wiley and Sons Ltd",

number = "4",

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TY - JOUR

T1 - Critical area analysis for design‐based yield improvement of vlsi circuits

AU - Schmitt‐Landsiedel, Doris

AU - Keitel‐Schulz, Doris

AU - Khare, Jitendra

AU - Griep, Susanne

AU - Maly, Wojciech

PY - 1995

Y1 - 1995

N2 - Yield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated for design based yield prediction and improvement. Experimental results for a typical CMOS process are provided.

AB - Yield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated for design based yield prediction and improvement. Experimental results for a typical CMOS process are provided.

KW - critical area

KW - defect simulation

KW - design‐based yield improvement

KW - failure analysis

KW - yield learning

UR - http://www.scopus.com/inward/record.url?scp=0029346651&partnerID=8YFLogxK

U2 - 10.1002/qre.4680110403

DO - 10.1002/qre.4680110403

M3 - Article

AN - SCOPUS:0029346651

SN - 0748-8017

VL - 11

SP - 227

EP - 232

JO - Quality and Reliability Engineering International

JF - Quality and Reliability Engineering International

IS - 4

ER -

Critical area analysis for design‐based yield improvement of vlsi circuits

Abstract

Keywords

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