CPU-independent assembler in an FPGA

Georg Acher, Carsten Trinitis, Rainer Buchty

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

We describe a system which enables FPGAs to generate machine code for various CPUs, similar to a conventional assembler. Such conversion from intermediate code to a CPU's native code can be used as the last step in just-in-time compilation for virtual machines like the Java Virtual Machine. The translation system itself and the FPGA logic are independent of the actual target CPU and can be used with both CISC and RISC CPUs. Due to an extended table lookup, the resulting code is very efficient and gains from pre-calculation of selected constants in the FPGA assembler.

Original languageEnglish
Title of host publicationProceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
Pages519-522
Number of pages4
DOIs
StatePublished - 2005
Event2005 International Conference on Field Programmable Logic and Applications, FPL - Tampere, Finland
Duration: 24 Aug 200526 Aug 2005

Publication series

NameProceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
Volume2005

Conference

Conference2005 International Conference on Field Programmable Logic and Applications, FPL
Country/TerritoryFinland
CityTampere
Period24/08/0526/08/05

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