TY - GEN
T1 - CPU-independent assembler in an FPGA
AU - Acher, Georg
AU - Trinitis, Carsten
AU - Buchty, Rainer
PY - 2005
Y1 - 2005
N2 - We describe a system which enables FPGAs to generate machine code for various CPUs, similar to a conventional assembler. Such conversion from intermediate code to a CPU's native code can be used as the last step in just-in-time compilation for virtual machines like the Java Virtual Machine. The translation system itself and the FPGA logic are independent of the actual target CPU and can be used with both CISC and RISC CPUs. Due to an extended table lookup, the resulting code is very efficient and gains from pre-calculation of selected constants in the FPGA assembler.
AB - We describe a system which enables FPGAs to generate machine code for various CPUs, similar to a conventional assembler. Such conversion from intermediate code to a CPU's native code can be used as the last step in just-in-time compilation for virtual machines like the Java Virtual Machine. The translation system itself and the FPGA logic are independent of the actual target CPU and can be used with both CISC and RISC CPUs. Due to an extended table lookup, the resulting code is very efficient and gains from pre-calculation of selected constants in the FPGA assembler.
UR - http://www.scopus.com/inward/record.url?scp=33746898647&partnerID=8YFLogxK
U2 - 10.1109/FPL.2005.1515775
DO - 10.1109/FPL.2005.1515775
M3 - Conference contribution
AN - SCOPUS:33746898647
SN - 0780393627
SN - 9780780393622
T3 - Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
SP - 519
EP - 522
BT - Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL
T2 - 2005 International Conference on Field Programmable Logic and Applications, FPL
Y2 - 24 August 2005 through 26 August 2005
ER -