TY - GEN
T1 - Contradiction Analysis for Inconsistent Formal Models
AU - Przigoda, Nils
AU - Wille, Robert
AU - Drechsler, Rolf
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/8/13
Y1 - 2015/8/13
N2 - Modeling languages such as UML or SysML in combination with constraint languages such as OCL allow for an abstract description of a system prior to its implementation. But the resulting system models can be highly non-trivial and, hence, errors in the descriptions can easily arise. In particular, too strong restrictions leading to an inconsistent model are common. Motivated by this, researchers and engineers developed methods for the validation and verification of given formal models. However, while these methods are efficient to detect the existence of an inconsistency, the designer is usually left alone to identify the reasons for it. In this contribution, we propose an automatic method which efficiently determines reasons explaining the contradiction in an inconsistent UML/OCL model. For this purpose, all constraints causing the contradiction are comprehensibly analyzed. By this, the designer is aided during the debugging of his/her model.
AB - Modeling languages such as UML or SysML in combination with constraint languages such as OCL allow for an abstract description of a system prior to its implementation. But the resulting system models can be highly non-trivial and, hence, errors in the descriptions can easily arise. In particular, too strong restrictions leading to an inconsistent model are common. Motivated by this, researchers and engineers developed methods for the validation and verification of given formal models. However, while these methods are efficient to detect the existence of an inconsistency, the designer is usually left alone to identify the reasons for it. In this contribution, we propose an automatic method which efficiently determines reasons explaining the contradiction in an inconsistent UML/OCL model. For this purpose, all constraints causing the contradiction are comprehensibly analyzed. By this, the designer is aided during the debugging of his/her model.
UR - https://www.scopus.com/pages/publications/84952715696
U2 - 10.1109/DDECS.2015.52
DO - 10.1109/DDECS.2015.52
M3 - Conference contribution
AN - SCOPUS:84952715696
T3 - Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
SP - 171
EP - 176
BT - Proceedings - 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
A2 - Vierhaus, Heinrich Theodor
A2 - Stamenkovic, Zoran
A2 - Pleskacz, Witold
A2 - Raik, Jaan
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2015
Y2 - 22 April 2015 through 24 April 2015
ER -