Contradiction analysis for constraint-based random simulation

Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

Constraint-based random simulation is state-of-the-art in verification of multi-million gate industrial designs. This method is based on stimulus generation by constraint solving. The resulting stimuli will particularly cover corner case test scenarios which are usually hard to identify manually by the verification engineer. Consequently, constraint-based random simulation will catch corner case bugs that would remain undetected otherwise. Therefore, the quality of design verification is increased significantly. However, in the process of constraint specification for a specific test scenario, the verification engineer is faced with the problem of over-constraining, i.e. the overall constraint specified for a test scenario has no solution. In this case the root cause of the contradiction has to be identified and resolved. Given the complexity of constraints used to describe test scenarios, this can be a very time-consuming process. In this paper we propose a fully automated contradiction analysis method. Our method determines all "non relevant" constraints and computes all reasons that lead to the over-constraining. Thus, we pinpoint the verification engineer to exactly the sets of constraints that have to be considered to resolve the over-constraining. Experiments have been conducted in a real-life SystemC-based verification environment at AMD Dresden Design Center. They demonstrate a significant reduction of the constraint contradiction debug time.

Original languageEnglish
Title of host publicationProceedings - 2008 Forum on Specification, Verification and Design Languages, FDL'08
Pages130-135
Number of pages6
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 Forum on Specification, Verification and Design Languages, FDL'08 - Stuttgart, Germany
Duration: 23 Sep 200825 Sep 2008

Publication series

NameProceedings - 2008 Forum on Specification, Verification and Design Languages, FDL'08

Conference

Conference2008 Forum on Specification, Verification and Design Languages, FDL'08
Country/TerritoryGermany
CityStuttgart
Period23/09/0825/09/08

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